Search

William B. Partridge

Examiner (ID: 7131, Phone: (571)270-1402 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2812, 2183
Total Applications
514
Issued Applications
410
Pending Applications
4
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16607959 [patent_doc_number] => 10908963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Deterministic real time business application processing in a service-oriented architecture [patent_app_type] => utility [patent_app_number] => 15/222226 [patent_app_country] => US [patent_app_date] => 2016-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5676 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15222226 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/222226
Deterministic real time business application processing in a service-oriented architecture Jul 27, 2016 Issued
Array ( [id] => 14917745 [patent_doc_number] => 10430192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Vector processing using loops of dynamic vector length [patent_app_type] => utility [patent_app_number] => 15/748734 [patent_app_country] => US [patent_app_date] => 2016-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 11421 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15748734 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/748734
Vector processing using loops of dynamic vector length Jul 27, 2016 Issued
Array ( [id] => 12094428 [patent_doc_number] => 20170351521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'FETCHED DATA IN AN ULTRA-SHORT PIPED LOAD STORE UNIT' [patent_app_type] => utility [patent_app_number] => 15/173078 [patent_app_country] => US [patent_app_date] => 2016-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5566 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15173078 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/173078
Fetched data in an ultra-short piped load store unit Jun 2, 2016 Issued
Array ( [id] => 12094425 [patent_doc_number] => 20170351518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'COMMUNICATION BETWEEN THREADS OF MULTI-THREAD PROCESSOR' [patent_app_type] => utility [patent_app_number] => 15/172885 [patent_app_country] => US [patent_app_date] => 2016-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6114 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15172885 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/172885
Communication between threads of multi-thread processor Jun 2, 2016 Issued
Array ( [id] => 12094427 [patent_doc_number] => 20170351520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'THREAD SWITCHING IN MICROPROCESSOR WITHOUT FULL SAVE AND RESTORE OF REGISTER FILE' [patent_app_type] => utility [patent_app_number] => 15/172864 [patent_app_country] => US [patent_app_date] => 2016-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7369 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15172864 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/172864
Thread switching in microprocessor without full save and restore of register file Jun 2, 2016 Issued
Array ( [id] => 15854669 [patent_doc_number] => 10642618 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-05-05 [patent_title] => Callgraph signature prefetch [patent_app_type] => utility [patent_app_number] => 15/171316 [patent_app_country] => US [patent_app_date] => 2016-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8850 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15171316 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/171316
Callgraph signature prefetch Jun 1, 2016 Issued
Array ( [id] => 12146719 [patent_doc_number] => 09880972 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-30 [patent_title] => 'Computer subsystem and computer system with composite nodes in an interconnection structure' [patent_app_type] => utility [patent_app_number] => 15/150419 [patent_app_country] => US [patent_app_date] => 2016-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5189 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15150419 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/150419
Computer subsystem and computer system with composite nodes in an interconnection structure May 8, 2016 Issued
Array ( [id] => 11745670 [patent_doc_number] => 20170199743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-13 [patent_title] => 'SELECTIVE SUPPRESSION OF INSTRUCTION CACHE-RELATED DIRECTORY ACCESS' [patent_app_type] => utility [patent_app_number] => 15/135891 [patent_app_country] => US [patent_app_date] => 2016-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10315 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15135891 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/135891
Selective suppression of instruction cache-related directory access Apr 21, 2016 Issued
Array ( [id] => 12114235 [patent_doc_number] => 09870228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-16 [patent_title] => 'Prioritising of instruction fetching in microprocessor systems' [patent_app_type] => utility [patent_app_number] => 15/134510 [patent_app_country] => US [patent_app_date] => 2016-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4489 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15134510 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/134510
Prioritising of instruction fetching in microprocessor systems Apr 20, 2016 Issued
Array ( [id] => 11109662 [patent_doc_number] => 20160306631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-20 [patent_title] => 'PROVIDING CODE SECTIONS FOR MATRIX OF ARITHMETIC LOGIC UNITS IN A PROCESSOR' [patent_app_type] => utility [patent_app_number] => 15/130852 [patent_app_country] => US [patent_app_date] => 2016-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 35847 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15130852 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/130852
PROVIDING CODE SECTIONS FOR MATRIX OF ARITHMETIC LOGIC UNITS IN A PROCESSOR Apr 14, 2016 Abandoned
Array ( [id] => 11019774 [patent_doc_number] => 20160216727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-28 [patent_title] => 'VARIABLE CLOCKED SERIAL ARRAY PROCESSOR' [patent_app_type] => utility [patent_app_number] => 15/092114 [patent_app_country] => US [patent_app_date] => 2016-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8134 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15092114 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/092114
Variable clocked serial array processor Apr 5, 2016 Issued
Array ( [id] => 12591936 [patent_doc_number] => 20180089141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => DATA PROCESSING DEVICE [patent_app_type] => utility [patent_app_number] => 15/564039 [patent_app_country] => US [patent_app_date] => 2016-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9250 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 381 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15564039 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/564039
Data processing device Apr 5, 2016 Issued
Array ( [id] => 11973279 [patent_doc_number] => 20170277433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-28 [patent_title] => 'MASK PATTERNS GENERATED IN MEMORY FROM SEED VECTORS' [patent_app_type] => utility [patent_app_number] => 15/081551 [patent_app_country] => US [patent_app_date] => 2016-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 18326 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15081551 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/081551
Mask patterns generated in memory from seed vectors Mar 24, 2016 Issued
Array ( [id] => 11801307 [patent_doc_number] => 09542183 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => 'Branch synthetic generation across multiple microarchitecture generations' [patent_app_type] => utility [patent_app_number] => 15/060633 [patent_app_country] => US [patent_app_date] => 2016-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5902 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15060633 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/060633
Branch synthetic generation across multiple microarchitecture generations Mar 3, 2016 Issued
Array ( [id] => 17046688 [patent_doc_number] => 11099868 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => System and method for translating a guest instruction of a guest architecture into at least one host instruction of a host architecture [patent_app_type] => utility [patent_app_number] => 15/565489 [patent_app_country] => US [patent_app_date] => 2016-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 11194 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15565489 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/565489
System and method for translating a guest instruction of a guest architecture into at least one host instruction of a host architecture Mar 3, 2016 Issued
Array ( [id] => 14061751 [patent_doc_number] => 10235168 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-19 [patent_title] => Load register on condition immediate or immediate instruction [patent_app_type] => utility [patent_app_number] => 15/008684 [patent_app_country] => US [patent_app_date] => 2016-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6749 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15008684 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/008684
Load register on condition immediate or immediate instruction Jan 27, 2016 Issued
Array ( [id] => 12194566 [patent_doc_number] => 09898296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Selective suppression of instruction translation lookaside buffer (ITLB) access' [patent_app_type] => utility [patent_app_number] => 14/990989 [patent_app_country] => US [patent_app_date] => 2016-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 10373 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14990989 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/990989
Selective suppression of instruction translation lookaside buffer (ITLB) access Jan 7, 2016 Issued
Array ( [id] => 10637382 [patent_doc_number] => 09354885 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-31 [patent_title] => 'Selective suppression of instruction cache-related directory access' [patent_app_type] => utility [patent_app_number] => 14/990984 [patent_app_country] => US [patent_app_date] => 2016-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 10315 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14990984 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/990984
Selective suppression of instruction cache-related directory access Jan 7, 2016 Issued
Array ( [id] => 12018851 [patent_doc_number] => 09811558 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-11-07 [patent_title] => 'Apparatus and method for parallel processing of a query' [patent_app_type] => utility [patent_app_number] => 14/973615 [patent_app_country] => US [patent_app_date] => 2015-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3526 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14973615 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/973615
Apparatus and method for parallel processing of a query Dec 16, 2015 Issued
Array ( [id] => 12018851 [patent_doc_number] => 09811558 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-11-07 [patent_title] => 'Apparatus and method for parallel processing of a query' [patent_app_type] => utility [patent_app_number] => 14/973615 [patent_app_country] => US [patent_app_date] => 2015-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3526 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14973615 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/973615
Apparatus and method for parallel processing of a query Dec 16, 2015 Issued
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