Search

William B. Partridge

Examiner (ID: 9488, Phone: (571)270-1402 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2812, 2183
Total Applications
515
Issued Applications
410
Pending Applications
5
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7631405 [patent_doc_number] => 06635527 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Metal-insulator-metal capacitor' [patent_app_type] => B1 [patent_app_number] => 09/318867 [patent_app_country] => US [patent_app_date] => 1999-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2683 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/635/06635527.pdf [firstpage_image] =>[orig_patent_app_number] => 09318867 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/318867
Metal-insulator-metal capacitor May 25, 1999 Issued
Array ( [id] => 1578355 [patent_doc_number] => 06448190 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Method and apparatus for fabrication of integrated circuit by selective deposition of precursor liquid' [patent_app_type] => B1 [patent_app_number] => 09/316917 [patent_app_country] => US [patent_app_date] => 1999-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 8744 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/448/06448190.pdf [firstpage_image] =>[orig_patent_app_number] => 09316917 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/316917
Method and apparatus for fabrication of integrated circuit by selective deposition of precursor liquid May 20, 1999 Issued
Array ( [id] => 4259330 [patent_doc_number] => 06258700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Silicide agglomeration fuse device' [patent_app_type] => 1 [patent_app_number] => 9/313830 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8740 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258700.pdf [firstpage_image] =>[orig_patent_app_number] => 313830 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/313830
Silicide agglomeration fuse device May 17, 1999 Issued
Array ( [id] => 4325240 [patent_doc_number] => 06329280 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Interim oxidation of silsesquioxane dielectric for dual damascene process' [patent_app_type] => 1 [patent_app_number] => 9/311470 [patent_app_country] => US [patent_app_date] => 1999-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3771 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329280.pdf [firstpage_image] =>[orig_patent_app_number] => 311470 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/311470
Interim oxidation of silsesquioxane dielectric for dual damascene process May 12, 1999 Issued
Array ( [id] => 4327419 [patent_doc_number] => 06319825 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Metallization process of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/310820 [patent_app_country] => US [patent_app_date] => 1999-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 4084 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/319/06319825.pdf [firstpage_image] =>[orig_patent_app_number] => 310820 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/310820
Metallization process of semiconductor device May 11, 1999 Issued
Array ( [id] => 4155827 [patent_doc_number] => 06156613 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Method to form MOSFET with an elevated source/drain' [patent_app_type] => 1 [patent_app_number] => 9/307630 [patent_app_country] => US [patent_app_date] => 1999-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2735 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/156/06156613.pdf [firstpage_image] =>[orig_patent_app_number] => 307630 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/307630
Method to form MOSFET with an elevated source/drain May 6, 1999 Issued
Array ( [id] => 1477743 [patent_doc_number] => 06344414 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Chemical-mechanical polishing system having a bi-material wafer backing film assembly' [patent_app_type] => B1 [patent_app_number] => 09/303470 [patent_app_country] => US [patent_app_date] => 1999-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3408 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/344/06344414.pdf [firstpage_image] =>[orig_patent_app_number] => 09303470 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/303470
Chemical-mechanical polishing system having a bi-material wafer backing film assembly Apr 29, 1999 Issued
Array ( [id] => 1474418 [patent_doc_number] => 06387736 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Method and structure for bonding layers in a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/299687 [patent_app_country] => US [patent_app_date] => 1999-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2823 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/387/06387736.pdf [firstpage_image] =>[orig_patent_app_number] => 09299687 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/299687
Method and structure for bonding layers in a semiconductor device Apr 25, 1999 Issued
Array ( [id] => 1545452 [patent_doc_number] => 06444588 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Anti-reflective coatings and methods regarding same' [patent_app_type] => B1 [patent_app_number] => 09/299357 [patent_app_country] => US [patent_app_date] => 1999-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 9007 [patent_no_of_claims] => 78 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/444/06444588.pdf [firstpage_image] =>[orig_patent_app_number] => 09299357 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/299357
Anti-reflective coatings and methods regarding same Apr 25, 1999 Issued
Array ( [id] => 4300937 [patent_doc_number] => 06184549 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Trench storage dynamic random access memory cell with vertical transfer device' [patent_app_type] => 1 [patent_app_number] => 9/296807 [patent_app_country] => US [patent_app_date] => 1999-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2166 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184549.pdf [firstpage_image] =>[orig_patent_app_number] => 296807 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/296807
Trench storage dynamic random access memory cell with vertical transfer device Apr 22, 1999 Issued
Array ( [id] => 4351070 [patent_doc_number] => 06285070 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Method of forming semiconductor die with integral decoupling capacitor' [patent_app_type] => 1 [patent_app_number] => 9/298159 [patent_app_country] => US [patent_app_date] => 1999-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2795 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285070.pdf [firstpage_image] =>[orig_patent_app_number] => 298159 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/298159
Method of forming semiconductor die with integral decoupling capacitor Apr 22, 1999 Issued
Array ( [id] => 4424844 [patent_doc_number] => 06225698 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Method for making semiconductor devices having gradual slope contacts' [patent_app_type] => 1 [patent_app_number] => 9/295437 [patent_app_country] => US [patent_app_date] => 1999-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4920 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225698.pdf [firstpage_image] =>[orig_patent_app_number] => 295437 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/295437
Method for making semiconductor devices having gradual slope contacts Apr 19, 1999 Issued
Array ( [id] => 1435865 [patent_doc_number] => 06355508 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Method for forming electrostatic discharge protection device having a graded junction' [patent_app_type] => B1 [patent_app_number] => 09/290720 [patent_app_country] => US [patent_app_date] => 1999-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 5573 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/355/06355508.pdf [firstpage_image] =>[orig_patent_app_number] => 09290720 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/290720
Method for forming electrostatic discharge protection device having a graded junction Apr 11, 1999 Issued
Array ( [id] => 1469909 [patent_doc_number] => 06407000 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Method and apparatuses for making and using bi-modal abrasive slurries for mechanical and chemical-mechanical planarization of microelectronic-device substrate assemblies' [patent_app_type] => B1 [patent_app_number] => 09/289790 [patent_app_country] => US [patent_app_date] => 1999-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4330 [patent_no_of_claims] => 87 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/407/06407000.pdf [firstpage_image] =>[orig_patent_app_number] => 09289790 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/289790
Method and apparatuses for making and using bi-modal abrasive slurries for mechanical and chemical-mechanical planarization of microelectronic-device substrate assemblies Apr 8, 1999 Issued
Array ( [id] => 4271025 [patent_doc_number] => 06323085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'High coupling split-gate transistor and method for its formation' [patent_app_type] => 1 [patent_app_number] => 9/285667 [patent_app_country] => US [patent_app_date] => 1999-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2979 [patent_no_of_claims] => 75 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323085.pdf [firstpage_image] =>[orig_patent_app_number] => 285667 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/285667
High coupling split-gate transistor and method for its formation Apr 4, 1999 Issued
Array ( [id] => 7631352 [patent_doc_number] => 06635580 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Apparatus and method for controlling wafer temperature in a plasma etcher' [patent_app_type] => B1 [patent_app_number] => 09/283037 [patent_app_country] => US [patent_app_date] => 1999-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3795 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/635/06635580.pdf [firstpage_image] =>[orig_patent_app_number] => 09283037 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/283037
Apparatus and method for controlling wafer temperature in a plasma etcher Mar 31, 1999 Issued
Array ( [id] => 4401206 [patent_doc_number] => 06297526 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Process for producing barrier-free semiconductor memory configurations' [patent_app_type] => 1 [patent_app_number] => 9/282097 [patent_app_country] => US [patent_app_date] => 1999-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 5164 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297526.pdf [firstpage_image] =>[orig_patent_app_number] => 282097 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/282097
Process for producing barrier-free semiconductor memory configurations Mar 29, 1999 Issued
Array ( [id] => 4389636 [patent_doc_number] => 06262445 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'SiC sidewall process' [patent_app_type] => 1 [patent_app_number] => 9/276047 [patent_app_country] => US [patent_app_date] => 1999-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1719 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/262/06262445.pdf [firstpage_image] =>[orig_patent_app_number] => 276047 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/276047
SiC sidewall process Mar 24, 1999 Issued
Array ( [id] => 1253383 [patent_doc_number] => 06670270 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-30 [patent_title] => 'Semiconductor device manufacturing apparatus and semiconductor device manufacturing method' [patent_app_type] => B1 [patent_app_number] => 09/273627 [patent_app_country] => US [patent_app_date] => 1999-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 6762 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/670/06670270.pdf [firstpage_image] =>[orig_patent_app_number] => 09273627 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/273627
Semiconductor device manufacturing apparatus and semiconductor device manufacturing method Mar 22, 1999 Issued
Array ( [id] => 1378504 [patent_doc_number] => 06555408 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Methods for transferring elements from a template to a substrate' [patent_app_type] => B1 [patent_app_number] => 09/270157 [patent_app_country] => US [patent_app_date] => 1999-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 5272 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/555/06555408.pdf [firstpage_image] =>[orig_patent_app_number] => 09270157 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/270157
Methods for transferring elements from a template to a substrate Mar 15, 1999 Issued
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