Search

William B. Partridge

Examiner (ID: 8836)

Most Active Art Unit
2183
Art Unit(s)
2812, 2183
Total Applications
515
Issued Applications
410
Pending Applications
5
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14825197 [patent_doc_number] => 10409606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-10 [patent_title] => Verifying branch targets [patent_app_type] => utility [patent_app_number] => 14/752356 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13322 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14752356 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/752356
Verifying branch targets Jun 25, 2015 Issued
Array ( [id] => 13679485 [patent_doc_number] => 20160378479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => DECOUPLED PROCESSOR INSTRUCTION WINDOW AND OPERAND BUFFER [patent_app_type] => utility [patent_app_number] => 14/752724 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8304 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14752724 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/752724
Decoupled processor instruction window and operand buffer Jun 25, 2015 Issued
Array ( [id] => 12352074 [patent_doc_number] => 09952867 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-24 [patent_title] => Mapping instruction blocks based on block size [patent_app_type] => utility [patent_app_number] => 14/752768 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8341 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14752768 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/752768
Mapping instruction blocks based on block size Jun 25, 2015 Issued
Array ( [id] => 12966955 [patent_doc_number] => 09875213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-23 [patent_title] => Methods, apparatus, instructions and logic to provide vector packed histogram functionality [patent_app_type] => utility [patent_app_number] => 14/752054 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 34 [patent_no_of_words] => 21854 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14752054 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/752054
Methods, apparatus, instructions and logic to provide vector packed histogram functionality Jun 25, 2015 Issued
Array ( [id] => 12331662 [patent_doc_number] => 09946548 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-17 [patent_title] => Age-based management of instruction blocks in a processor instruction window [patent_app_type] => utility [patent_app_number] => 14/752747 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8291 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14752747 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/752747
Age-based management of instruction blocks in a processor instruction window Jun 25, 2015 Issued
Array ( [id] => 13679461 [patent_doc_number] => 20160378467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => PERSISTENT COMMIT PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 14/751892 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21427 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14751892 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/751892
Persistent commit processors, methods, systems, and instructions Jun 25, 2015 Issued
Array ( [id] => 13679513 [patent_doc_number] => 20160378493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => BULK ALLOCATION OF INSTRUCTION BLOCKS TO A PROCESSOR INSTRUCTION WINDOW [patent_app_type] => utility [patent_app_number] => 14/752685 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8330 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14752685 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/752685
Bulk allocation of instruction blocks to a processor instruction window Jun 25, 2015 Issued
Array ( [id] => 10778557 [patent_doc_number] => 20160124713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-05 [patent_title] => 'FAST, ENERGY-EFFICIENT EXPONENTIAL COMPUTATIONS IN SIMD ARCHITECTURES' [patent_app_type] => utility [patent_app_number] => 14/745499 [patent_app_country] => US [patent_app_date] => 2015-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6543 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14745499 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/745499
FAST, ENERGY-EFFICIENT EXPONENTIAL COMPUTATIONS IN SIMD ARCHITECTURES Jun 21, 2015 Abandoned
Array ( [id] => 13157843 [patent_doc_number] => 10095647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => Accelerator architecture on a programmable platform [patent_app_type] => utility [patent_app_number] => 14/725811 [patent_app_country] => US [patent_app_date] => 2015-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 5598 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14725811 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/725811
Accelerator architecture on a programmable platform May 28, 2015 Issued
Array ( [id] => 13017277 [patent_doc_number] => 10031753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-24 [patent_title] => Computer systems and methods for executing contexts with autonomous functional units [patent_app_type] => utility [patent_app_number] => 14/719390 [patent_app_country] => US [patent_app_date] => 2015-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4881 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14719390 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/719390
Computer systems and methods for executing contexts with autonomous functional units May 21, 2015 Issued
Array ( [id] => 10368838 [patent_doc_number] => 20150253843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'DYNAMIC ENERGY SAVINGS FOR DIGITAL SIGNAL PROCESSOR MODULES USING PLURAL ENERGY SAVINGS STATES' [patent_app_type] => utility [patent_app_number] => 14/715049 [patent_app_country] => US [patent_app_date] => 2015-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8028 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14715049 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/715049
Dynamic energy savings for digital signal processor modules using plural energy savings states May 17, 2015 Issued
Array ( [id] => 11200081 [patent_doc_number] => 09430293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'Deterministic real time business application processing in a service-oriented architecture' [patent_app_type] => utility [patent_app_number] => 14/696972 [patent_app_country] => US [patent_app_date] => 2015-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5718 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14696972 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/696972
Deterministic real time business application processing in a service-oriented architecture Apr 26, 2015 Issued
Array ( [id] => 10392898 [patent_doc_number] => 20150277905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'ARITHMETIC PROCESSING UNIT AND CONTROL METHOD FOR ARITHMETIC PROCESSING UNIT' [patent_app_type] => utility [patent_app_number] => 14/665405 [patent_app_country] => US [patent_app_date] => 2015-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11349 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14665405 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/665405
ARITHMETIC PROCESSING UNIT AND CONTROL METHOD FOR ARITHMETIC PROCESSING UNIT Mar 22, 2015 Abandoned
Array ( [id] => 11700716 [patent_doc_number] => 09690630 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-27 [patent_title] => 'Hardware accelerator test harness generation' [patent_app_type] => utility [patent_app_number] => 14/637354 [patent_app_country] => US [patent_app_date] => 2015-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 40 [patent_no_of_words] => 12551 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14637354 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/637354
Hardware accelerator test harness generation Mar 2, 2015 Issued
Array ( [id] => 14265279 [patent_doc_number] => 10282203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Methods and devices for discovering multiple instances of recurring values within a vector with an application to sorting [patent_app_type] => utility [patent_app_number] => 15/548083 [patent_app_country] => US [patent_app_date] => 2015-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6760 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15548083 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/548083
Methods and devices for discovering multiple instances of recurring values within a vector with an application to sorting Feb 4, 2015 Issued
Array ( [id] => 10250193 [patent_doc_number] => 20150135189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'SOFTWARE-BASED THREAD REMAPPING FOR POWER SAVINGS' [patent_app_type] => utility [patent_app_number] => 14/582757 [patent_app_country] => US [patent_app_date] => 2014-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7253 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14582757 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/582757
SOFTWARE-BASED THREAD REMAPPING FOR POWER SAVINGS Dec 23, 2014 Abandoned
Array ( [id] => 10630445 [patent_doc_number] => 09348595 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-24 [patent_title] => 'Run-time code parallelization with continuous monitoring of repetitive instruction sequences' [patent_app_type] => utility [patent_app_number] => 14/578516 [patent_app_country] => US [patent_app_date] => 2014-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 6385 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14578516 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/578516
Run-time code parallelization with continuous monitoring of repetitive instruction sequences Dec 21, 2014 Issued
Array ( [id] => 10258092 [patent_doc_number] => 20150143089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'SYSTEM PERFORMANCE ENHANCEMENT WITH SMI ON MULTI-CORE SYSTEMS' [patent_app_type] => utility [patent_app_number] => 14/549272 [patent_app_country] => US [patent_app_date] => 2014-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6645 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14549272 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/549272
System performance enhancement with SMI on multi-core systems Nov 19, 2014 Issued
Array ( [id] => 12173780 [patent_doc_number] => 09891923 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'Loop predictor-directed loop buffer' [patent_app_type] => utility [patent_app_number] => 14/534841 [patent_app_country] => US [patent_app_date] => 2014-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8450 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14534841 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/534841
Loop predictor-directed loop buffer Nov 5, 2014 Issued
Array ( [id] => 10778553 [patent_doc_number] => 20160124709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-05 [patent_title] => 'FAST, ENERGY-EFFICIENT EXPONENTIAL COMPUTATIONS IN SIMD ARCHITECTURES' [patent_app_type] => utility [patent_app_number] => 14/532312 [patent_app_country] => US [patent_app_date] => 2014-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6517 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14532312 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/532312
FAST, ENERGY-EFFICIENT EXPONENTIAL COMPUTATIONS IN SIMD ARCHITECTURES Nov 3, 2014 Abandoned
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