Search

William D Thomson

Supervisory Patent Examiner (ID: 5240, Phone: (571)272-3718 , Office: P/3769 )

Most Active Art Unit
2123
Art Unit(s)
3797, 2763, 3769, 3793, 2123, 2194, 2758
Total Applications
504
Issued Applications
156
Pending Applications
163
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1206325 [patent_doc_number] => 06721694 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-13 [patent_title] => 'Method and system for representing the depths of the floors of the oceans' [patent_app_type] => B1 [patent_app_number] => 09/170821 [patent_app_country] => US [patent_app_date] => 1998-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7328 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/721/06721694.pdf [firstpage_image] =>[orig_patent_app_number] => 09170821 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/170821
Method and system for representing the depths of the floors of the oceans Oct 12, 1998 Issued
Array ( [id] => 4349609 [patent_doc_number] => 06334100 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Method and apparatus for electronic circuit model correction' [patent_app_type] => 1 [patent_app_number] => 9/169502 [patent_app_country] => US [patent_app_date] => 1998-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 10907 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 28 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/334/06334100.pdf [firstpage_image] =>[orig_patent_app_number] => 169502 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/169502
Method and apparatus for electronic circuit model correction Oct 8, 1998 Issued
Array ( [id] => 6455450 [patent_doc_number] => 20020177911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'METHOD AND APPARATUS FOR DETERMINING AN ARRANGEMENT OF COMPONENTS' [patent_app_type] => new [patent_app_number] => 09/163752 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9457 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20020177911.pdf [firstpage_image] =>[orig_patent_app_number] => 09163752 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/163752
METHOD AND APPARATUS FOR DETERMINING AN ARRANGEMENT OF COMPONENTS Sep 29, 1998 Abandoned
Array ( [id] => 6908446 [patent_doc_number] => 20010011213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-02 [patent_title] => 'MODEM USING A DIGITAL SIGNAL PROCESSOR AND A SIGNAL BASED COMMAND SET' [patent_app_type] => new [patent_app_number] => 09/160332 [patent_app_country] => US [patent_app_date] => 1998-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 9723 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20010011213.pdf [firstpage_image] =>[orig_patent_app_number] => 09160332 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/160332
Modem using a digital signal processor and a signal based command set Sep 24, 1998 Issued
Array ( [id] => 1379475 [patent_doc_number] => 06574588 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-03 [patent_title] => 'Solid-state memory device that emulates a known storage device' [patent_app_type] => B1 [patent_app_number] => 09/159522 [patent_app_country] => US [patent_app_date] => 1998-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3819 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/574/06574588.pdf [firstpage_image] =>[orig_patent_app_number] => 09159522 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/159522
Solid-state memory device that emulates a known storage device Sep 22, 1998 Issued
09/142973 COMPUTER INPUT/OUTPUT DEVICE FOR SENORY COMMUNICATION Sep 17, 1998 Abandoned
Array ( [id] => 4308323 [patent_doc_number] => 06212486 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Method of identifying critical elements in fatigue analysis with von mises stress bounding and filtering modal displacement history using dynamic windowing' [patent_app_type] => 1 [patent_app_number] => 9/156195 [patent_app_country] => US [patent_app_date] => 1998-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2240 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212486.pdf [firstpage_image] =>[orig_patent_app_number] => 156195 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/156195
Method of identifying critical elements in fatigue analysis with von mises stress bounding and filtering modal displacement history using dynamic windowing Sep 16, 1998 Issued
Array ( [id] => 4377704 [patent_doc_number] => 06192330 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Method and apparatus for string model simulation of a physical semiconductor process including use of specific depth angles and segment list with removal of redundant segments' [patent_app_type] => 1 [patent_app_number] => 9/152390 [patent_app_country] => US [patent_app_date] => 1998-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 40 [patent_no_of_words] => 8506 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/192/06192330.pdf [firstpage_image] =>[orig_patent_app_number] => 152390 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/152390
Method and apparatus for string model simulation of a physical semiconductor process including use of specific depth angles and segment list with removal of redundant segments Sep 13, 1998 Issued
Array ( [id] => 896913 [patent_doc_number] => 07346479 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-18 [patent_title] => 'Selecting design points on parameter functions having first sum of constraint set and second sum of optimizing set to improve second sum within design constraints' [patent_app_type] => utility [patent_app_number] => 09/148392 [patent_app_country] => US [patent_app_date] => 1998-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6134 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/346/07346479.pdf [firstpage_image] =>[orig_patent_app_number] => 09148392 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/148392
Selecting design points on parameter functions having first sum of constraint set and second sum of optimizing set to improve second sum within design constraints Sep 3, 1998 Issued
Array ( [id] => 7622508 [patent_doc_number] => 06687658 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-03 [patent_title] => 'Apparatus and method for reduced-order modeling of time-varying systems and computer storage medium containing the same' [patent_app_type] => B1 [patent_app_number] => 09/144799 [patent_app_country] => US [patent_app_date] => 1998-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6922 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/687/06687658.pdf [firstpage_image] =>[orig_patent_app_number] => 09144799 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/144799
Apparatus and method for reduced-order modeling of time-varying systems and computer storage medium containing the same Aug 31, 1998 Issued
Array ( [id] => 4422211 [patent_doc_number] => 06311144 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Method and apparatus for designing and analyzing information systems using multi-layer mathematical models' [patent_app_type] => 1 [patent_app_number] => 9/127191 [patent_app_country] => US [patent_app_date] => 1998-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11068 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311144.pdf [firstpage_image] =>[orig_patent_app_number] => 127191 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/127191
Method and apparatus for designing and analyzing information systems using multi-layer mathematical models Jul 30, 1998 Issued
Array ( [id] => 4310573 [patent_doc_number] => 06212632 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Method and system for efficiently reducing the RAM footprint of software executing on an embedded computer system' [patent_app_type] => 1 [patent_app_number] => 9/127345 [patent_app_country] => US [patent_app_date] => 1998-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 5899 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212632.pdf [firstpage_image] =>[orig_patent_app_number] => 127345 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/127345
Method and system for efficiently reducing the RAM footprint of software executing on an embedded computer system Jul 30, 1998 Issued
Array ( [id] => 6908445 [patent_doc_number] => 20010011212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-02 [patent_title] => 'METHOD AND APPARATUS FOR GATE-LEVEL SIMULATION OF SYNTHESIZED REGISTER TRANSFER LEVEL DESIGN WITH SOURCE-LEVEL DEBUGGING' [patent_app_type] => new [patent_app_number] => 09/122493 [patent_app_country] => US [patent_app_date] => 1998-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7939 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20010011212.pdf [firstpage_image] =>[orig_patent_app_number] => 09122493 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/122493
Method and apparatus for gate-level simulation of synthesized register transfer level design with source-level debugging Jul 23, 1998 Issued
Array ( [id] => 4379518 [patent_doc_number] => 06256604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Memory integrated with logic on a semiconductor chip and method of designing the same' [patent_app_type] => 1 [patent_app_number] => 9/120999 [patent_app_country] => US [patent_app_date] => 1998-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 48 [patent_no_of_words] => 21797 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256604.pdf [firstpage_image] =>[orig_patent_app_number] => 120999 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/120999
Memory integrated with logic on a semiconductor chip and method of designing the same Jul 22, 1998 Issued
Array ( [id] => 4308353 [patent_doc_number] => 06212488 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Riser reactor simulation in catalytic cracking' [patent_app_type] => 1 [patent_app_number] => 9/119194 [patent_app_country] => US [patent_app_date] => 1998-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6976 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 361 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212488.pdf [firstpage_image] =>[orig_patent_app_number] => 119194 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/119194
Riser reactor simulation in catalytic cracking Jul 19, 1998 Issued
09/118702 SYSTEM AND METHOD FOR COLLABORATIVE DATA SHARING Jul 15, 1998 Abandoned
Array ( [id] => 1213954 [patent_doc_number] => 06714903 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Placement and routing of circuits using a combined processing/buffer cell' [patent_app_type] => B1 [patent_app_number] => 09/113995 [patent_app_country] => US [patent_app_date] => 1998-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6703 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/714/06714903.pdf [firstpage_image] =>[orig_patent_app_number] => 09113995 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/113995
Placement and routing of circuits using a combined processing/buffer cell Jul 9, 1998 Issued
Array ( [id] => 1443719 [patent_doc_number] => 06496791 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Interfaces for an open systems server providing tape drive emulation' [patent_app_type] => B1 [patent_app_number] => 09/111691 [patent_app_country] => US [patent_app_date] => 1998-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4197 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496791.pdf [firstpage_image] =>[orig_patent_app_number] => 09111691 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/111691
Interfaces for an open systems server providing tape drive emulation Jul 7, 1998 Issued
Array ( [id] => 1236091 [patent_doc_number] => 06694357 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-17 [patent_title] => 'Accessing, viewing and manipulation of references to non-modifiable data objects' [patent_app_type] => B1 [patent_app_number] => 09/109135 [patent_app_country] => US [patent_app_date] => 1998-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 27 [patent_no_of_words] => 7639 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/694/06694357.pdf [firstpage_image] =>[orig_patent_app_number] => 09109135 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/109135
Accessing, viewing and manipulation of references to non-modifiable data objects Jul 1, 1998 Issued
Array ( [id] => 4411007 [patent_doc_number] => 06298318 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Real-time IMU signal emulation method for test of Guidance Navigation and Control systems' [patent_app_type] => 1 [patent_app_number] => 9/108595 [patent_app_country] => US [patent_app_date] => 1998-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4918 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/298/06298318.pdf [firstpage_image] =>[orig_patent_app_number] => 108595 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/108595
Real-time IMU signal emulation method for test of Guidance Navigation and Control systems Jun 30, 1998 Issued
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