
William G. Jones
Examiner (ID: 12867)
| Most Active Art Unit | 1306 |
| Art Unit(s) | 1303, 1807, 2899, 1306, 1634, 1655 |
| Total Applications | 764 |
| Issued Applications | 601 |
| Pending Applications | 29 |
| Abandoned Applications | 134 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4544558
[patent_doc_number] => 07889582
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-02-15
[patent_title] => 'Segmented write bitline system and method'
[patent_app_type] => utility
[patent_app_number] => 12/046675
[patent_app_country] => US
[patent_app_date] => 2008-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2411
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/889/07889582.pdf
[firstpage_image] =>[orig_patent_app_number] => 12046675
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/046675 | Segmented write bitline system and method | Mar 11, 2008 | Issued |
Array
(
[id] => 4482255
[patent_doc_number] => 07907457
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-03-15
[patent_title] => 'Memory and voltage monitoring device thereof'
[patent_app_type] => utility
[patent_app_number] => 12/047151
[patent_app_country] => US
[patent_app_date] => 2008-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 4063
[patent_no_of_claims] => 14
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/907/07907457.pdf
[firstpage_image] =>[orig_patent_app_number] => 12047151
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/047151 | Memory and voltage monitoring device thereof | Mar 11, 2008 | Issued |
Array
(
[id] => 5513335
[patent_doc_number] => 20090213641
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-27
[patent_title] => 'MEMORY WITH ACTIVE MODE BACK-BIAS VOLTAGE CONTROL AND METHOD OF OPERATING SAME'
[patent_app_type] => utility
[patent_app_number] => 12/035601
[patent_app_country] => US
[patent_app_date] => 2008-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3340
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[pdf_file] => publications/A1/0213/20090213641.pdf
[firstpage_image] =>[orig_patent_app_number] => 12035601
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/035601 | MEMORY WITH ACTIVE MODE BACK-BIAS VOLTAGE CONTROL AND METHOD OF OPERATING SAME | Feb 21, 2008 | Abandoned |
Array
(
[id] => 4678174
[patent_doc_number] => 20080215805
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-04
[patent_title] => 'DIGITAL DATA BUFFER'
[patent_app_type] => utility
[patent_app_number] => 12/028637
[patent_app_country] => US
[patent_app_date] => 2008-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2636
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0215/20080215805.pdf
[firstpage_image] =>[orig_patent_app_number] => 12028637
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/028637 | Digital data buffer with phase aligner | Feb 7, 2008 | Issued |
Array
(
[id] => 56359
[patent_doc_number] => 07768852
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-08-03
[patent_title] => 'Precharge control circuit in semiconductor memory apparatus'
[patent_app_type] => utility
[patent_app_number] => 12/026415
[patent_app_country] => US
[patent_app_date] => 2008-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 6840
[patent_no_of_claims] => 19
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/768/07768852.pdf
[firstpage_image] =>[orig_patent_app_number] => 12026415
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/026415 | Precharge control circuit in semiconductor memory apparatus | Feb 4, 2008 | Issued |
Array
(
[id] => 5445273
[patent_doc_number] => 20090046499
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-02-19
[patent_title] => 'INTEGRATED CIRCUIT INCLUDING MEMORY HAVING LIMITED READ'
[patent_app_type] => utility
[patent_app_number] => 12/026249
[patent_app_country] => US
[patent_app_date] => 2008-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 5480
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[pdf_file] => publications/A1/0046/20090046499.pdf
[firstpage_image] =>[orig_patent_app_number] => 12026249
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/026249 | INTEGRATED CIRCUIT INCLUDING MEMORY HAVING LIMITED READ | Feb 4, 2008 | Abandoned |
Array
(
[id] => 4811906
[patent_doc_number] => 20080192537
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-14
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/026417
[patent_app_country] => US
[patent_app_date] => 2008-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2657
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0192/20080192537.pdf
[firstpage_image] =>[orig_patent_app_number] => 12026417
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/026417 | Semiconductor device and method for adjusting reference levels of reference cells | Feb 4, 2008 | Issued |
Array
(
[id] => 5526018
[patent_doc_number] => 20090196095
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-06
[patent_title] => 'MULTIPLE MEMORY CELLS AND METHOD'
[patent_app_type] => utility
[patent_app_number] => 12/026195
[patent_app_country] => US
[patent_app_date] => 2008-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4924
[patent_no_of_claims] => 26
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[pdf_file] => publications/A1/0196/20090196095.pdf
[firstpage_image] =>[orig_patent_app_number] => 12026195
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/026195 | Multiple memory cells with rectifying device | Feb 4, 2008 | Issued |
Array
(
[id] => 5440353
[patent_doc_number] => 20090091992
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-09
[patent_title] => 'SEMICONDUCTOR MEMORY APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 12/026449
[patent_app_country] => US
[patent_app_date] => 2008-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 4772
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[pdf_file] => publications/A1/0091/20090091992.pdf
[firstpage_image] =>[orig_patent_app_number] => 12026449
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/026449 | SEMICONDUCTOR MEMORY APPARATUS | Feb 4, 2008 | Abandoned |
Array
(
[id] => 4843320
[patent_doc_number] => 20080179728
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-31
[patent_title] => 'Laminated memory'
[patent_app_type] => utility
[patent_app_number] => 12/010839
[patent_app_country] => US
[patent_app_date] => 2008-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[patent_no_of_words] => 5873
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[pdf_file] => publications/A1/0179/20080179728.pdf
[firstpage_image] =>[orig_patent_app_number] => 12010839
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/010839 | Laminated memory | Jan 29, 2008 | Abandoned |
Array
(
[id] => 5354067
[patent_doc_number] => 20090185411
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-07-23
[patent_title] => 'INTEGRATED CIRCUIT INCLUDING DIODE MEMORY CELLS'
[patent_app_type] => utility
[patent_app_number] => 12/017581
[patent_app_country] => US
[patent_app_date] => 2008-01-22
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0185/20090185411.pdf
[firstpage_image] =>[orig_patent_app_number] => 12017581
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/017581 | INTEGRATED CIRCUIT INCLUDING DIODE MEMORY CELLS | Jan 21, 2008 | Abandoned |
Array
(
[id] => 5354085
[patent_doc_number] => 20090185429
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-07-23
[patent_title] => 'Non-volatile memory with single floating gate and method for operating the same'
[patent_app_type] => utility
[patent_app_number] => 12/010121
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[patent_app_date] => 2008-01-22
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[pdf_file] => publications/A1/0185/20090185429.pdf
[firstpage_image] =>[orig_patent_app_number] => 12010121
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/010121 | Non-volatile memory with single floating gate and method for operating the same | Jan 21, 2008 | Abandoned |
Array
(
[id] => 4620427
[patent_doc_number] => 08000151
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-08-16
[patent_title] => 'Semiconductor memory column decoder device and method'
[patent_app_type] => utility
[patent_app_number] => 12/008417
[patent_app_country] => US
[patent_app_date] => 2008-01-10
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/08/000/08000151.pdf
[firstpage_image] =>[orig_patent_app_number] => 12008417
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/008417 | Semiconductor memory column decoder device and method | Jan 9, 2008 | Issued |
Array
(
[id] => 5437838
[patent_doc_number] => 20090172425
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-07-02
[patent_title] => 'Digitally controlled dynamic power management unit for uninterruptible power supply'
[patent_app_type] => utility
[patent_app_number] => 12/006229
[patent_app_country] => US
[patent_app_date] => 2007-12-31
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[pdf_file] => publications/A1/0172/20090172425.pdf
[firstpage_image] =>[orig_patent_app_number] => 12006229
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/006229 | Digitally controlled dynamic power management unit for uninterruptible power supply | Dec 30, 2007 | Abandoned |
Array
(
[id] => 187086
[patent_doc_number] => 07646632
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-01-12
[patent_title] => 'Integrated circuit for setting a memory cell based on a reset current distribution'
[patent_app_type] => utility
[patent_app_number] => 11/962701
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[firstpage_image] =>[orig_patent_app_number] => 11962701
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/962701 | Integrated circuit for setting a memory cell based on a reset current distribution | Dec 20, 2007 | Issued |
Array
(
[id] => 5500722
[patent_doc_number] => 20090161410
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-06-25
[patent_title] => 'SEVEN TRANSISTOR SRAM CELL'
[patent_app_type] => utility
[patent_app_number] => 11/962713
[patent_app_country] => US
[patent_app_date] => 2007-12-21
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[firstpage_image] =>[orig_patent_app_number] => 11962713
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/962713 | SEVEN TRANSISTOR SRAM CELL | Dec 20, 2007 | Abandoned |
Array
(
[id] => 4696876
[patent_doc_number] => 20080219060
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-11
[patent_title] => 'DEVICE AND METHOD FOR INTERNAL VOLTAGE MONITORING'
[patent_app_type] => utility
[patent_app_number] => 11/962925
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/962925 | DEVICE AND METHOD FOR INTERNAL VOLTAGE MONITORING | Dec 20, 2007 | Abandoned |
Array
(
[id] => 4878292
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[patent_title] => 'REDUCTION OF POWER CONSUMPTION OF AN INTEGRATED ELECTRONIC SYSTEM COMPRISING DISTINCT STATIC RANDOM ACCESS RESOURCES FOR STORING DATA'
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Array
(
[id] => 5500783
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[patent_title] => 'Power supply device'
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[firstpage_image] =>[orig_patent_app_number] => 12004781
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/004781 | Power supply device | Dec 20, 2007 | Abandoned |
Array
(
[id] => 4662312
[patent_doc_number] => 20080253219
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-16
[patent_title] => 'ACTIVE DRIVER CONTROL CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 11/963035
[patent_app_country] => US
[patent_app_date] => 2007-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => publications/A1/0253/20080253219.pdf
[firstpage_image] =>[orig_patent_app_number] => 11963035
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/963035 | Active driver control circuit for semiconductor memory apparatus | Dec 20, 2007 | Issued |