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William G. Jones

Examiner (ID: 12867)

Most Active Art Unit
1306
Art Unit(s)
1303, 1807, 2899, 1306, 1634, 1655
Total Applications
764
Issued Applications
601
Pending Applications
29
Abandoned Applications
134

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6564402 [patent_doc_number] => 20100128512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-27 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE HAVING CROSS-POINT STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/089273 [patent_app_country] => US [patent_app_date] => 2006-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8532 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20100128512.pdf [firstpage_image] =>[orig_patent_app_number] => 12089273 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/089273
SEMICONDUCTOR MEMORY DEVICE HAVING CROSS-POINT STRUCTURE Sep 26, 2006 Abandoned
Array ( [id] => 4891327 [patent_doc_number] => 20080100424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'Semiconductor Apparatus and Method of Testing Semiconductor Apparatus' [patent_app_type] => utility [patent_app_number] => 11/662705 [patent_app_country] => US [patent_app_date] => 2006-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3024 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20080100424.pdf [firstpage_image] =>[orig_patent_app_number] => 11662705 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/662705
Semiconductor apparatus and testing method using different internal voltages to output binary signals Jun 26, 2006 Issued
Array ( [id] => 5163028 [patent_doc_number] => 20070284609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'METHOD AND APPARATUS FOR DRAIN PUMP POWER CONSERVATION' [patent_app_type] => utility [patent_app_number] => 11/423649 [patent_app_country] => US [patent_app_date] => 2006-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2159 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20070284609.pdf [firstpage_image] =>[orig_patent_app_number] => 11423649 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/423649
METHOD AND APPARATUS FOR DRAIN PUMP POWER CONSERVATION Jun 11, 2006 Abandoned
Array ( [id] => 4871910 [patent_doc_number] => 20080198644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'Data Storage Device' [patent_app_type] => utility [patent_app_number] => 11/917571 [patent_app_country] => US [patent_app_date] => 2006-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6017 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20080198644.pdf [firstpage_image] =>[orig_patent_app_number] => 11917571 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/917571
Card-like memory unit with separate read/write unit Jun 7, 2006 Issued
Array ( [id] => 5500754 [patent_doc_number] => 20090161442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-25 [patent_title] => 'Data Processing System' [patent_app_type] => utility [patent_app_number] => 12/085901 [patent_app_country] => US [patent_app_date] => 2005-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7940 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20090161442.pdf [firstpage_image] =>[orig_patent_app_number] => 12085901 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/085901
Apparatus and method for adjusting a supply voltage based on a read result Dec 1, 2005 Issued
Array ( [id] => 4732552 [patent_doc_number] => 20080049531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'Memory arrangement and method for operating such a memory arrangement' [patent_app_type] => utility [patent_app_number] => 10/577881 [patent_app_country] => US [patent_app_date] => 2004-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2707 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20080049531.pdf [firstpage_image] =>[orig_patent_app_number] => 10577881 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/577881
Memory arrangement and method for operating such a memory arrangement Oct 26, 2004 Abandoned
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