Search

William G. Wright

Examiner (ID: 2362)

Most Active Art Unit
1106
Art Unit(s)
1754, 1106
Total Applications
637
Issued Applications
554
Pending Applications
0
Abandoned Applications
83

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17338069 [patent_doc_number] => 20220004400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => FPGA-BASED DATA PROCESSING METHOD, APPARATUS, DEVICE AND MEDIUM [patent_app_type] => utility [patent_app_number] => 17/281259 [patent_app_country] => US [patent_app_date] => 2019-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4851 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17281259 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/281259
FPGA-BASED DATA PROCESSING METHOD, APPARATUS, DEVICE AND MEDIUM Aug 29, 2019 Abandoned
Array ( [id] => 16227569 [patent_doc_number] => 20200252686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-06 [patent_title] => STANDBY MODE SWITCHING METHOD, DEVICE, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 16/514614 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5541 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16514614 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/514614
STANDBY MODE SWITCHING METHOD, DEVICE, AND STORAGE MEDIUM Jul 16, 2019 Abandoned
Array ( [id] => 17422863 [patent_doc_number] => 11256317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Systems and methods for scheduling component activation [patent_app_type] => utility [patent_app_number] => 16/416066 [patent_app_country] => US [patent_app_date] => 2019-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8490 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16416066 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/416066
Systems and methods for scheduling component activation May 16, 2019 Issued
Array ( [id] => 16972069 [patent_doc_number] => 11068040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Clock gating unit for a transponder [patent_app_type] => utility [patent_app_number] => 16/406083 [patent_app_country] => US [patent_app_date] => 2019-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4368 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16406083 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/406083
Clock gating unit for a transponder May 7, 2019 Issued
Array ( [id] => 15214035 [patent_doc_number] => 20190369704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => COMPUTING DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/402565 [patent_app_country] => US [patent_app_date] => 2019-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7025 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16402565 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/402565
Computing device and method of operating the same May 2, 2019 Issued
Array ( [id] => 15886335 [patent_doc_number] => 10649511 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Scalable data collection for system management [patent_app_type] => utility [patent_app_number] => 16/397822 [patent_app_country] => US [patent_app_date] => 2019-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6910 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16397822 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/397822
Scalable data collection for system management Apr 28, 2019 Issued
Array ( [id] => 17621617 [patent_doc_number] => 11340671 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Protocol level control for system on a chip (SOC) agent reset and power management [patent_app_type] => utility [patent_app_number] => 16/368443 [patent_app_country] => US [patent_app_date] => 2019-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 14758 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16368443 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/368443
Protocol level control for system on a chip (SOC) agent reset and power management Mar 27, 2019 Issued
Array ( [id] => 14934447 [patent_doc_number] => 20190302861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => PROTOCOL LEVEL CONTROL FOR SYSTEM ON A CHIP (SOC) AGENT RESET AND POWER MANAGEMENT [patent_app_type] => utility [patent_app_number] => 16/368418 [patent_app_country] => US [patent_app_date] => 2019-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14758 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16368418 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/368418
PROTOCOL LEVEL CONTROL FOR SYSTEM ON A CHIP (SOC) AGENT RESET AND POWER MANAGEMENT Mar 27, 2019 Abandoned
Array ( [id] => 14936277 [patent_doc_number] => 20190303777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => PROTOCOL LEVEL CONTROL FOR SYSTEM ON A CHIP (SOC) AGENT RESET AND POWER MANAGEMENT [patent_app_type] => utility [patent_app_number] => 16/368392 [patent_app_country] => US [patent_app_date] => 2019-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14759 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16368392 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/368392
PROTOCOL LEVEL CONTROL FOR SYSTEM ON A CHIP (SOC) AGENT RESET AND POWER MANAGEMENT Mar 27, 2019 Abandoned
Array ( [id] => 14871925 [patent_doc_number] => 20190286204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => ELECTRONIC DEVICE INCLUDING POWER SUPPLY AND METHOD TO BE EXECUTED BY ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/352891 [patent_app_country] => US [patent_app_date] => 2019-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16352891 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/352891
Electronic device including power supply and method to be executed by electronic device Mar 13, 2019 Issued
Array ( [id] => 17379603 [patent_doc_number] => 11237617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Arbitration techniques for managed memory [patent_app_type] => utility [patent_app_number] => 16/293295 [patent_app_country] => US [patent_app_date] => 2019-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 19853 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 370 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16293295 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/293295
Arbitration techniques for managed memory Mar 4, 2019 Issued
Array ( [id] => 16299544 [patent_doc_number] => 20200285267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => CLOCK GLITCH MITIGATION APPARATUS AND METHOD [patent_app_type] => utility [patent_app_number] => 16/292204 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7116 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16292204 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/292204
Clock glitch mitigation apparatus and method Mar 3, 2019 Issued
Array ( [id] => 18997869 [patent_doc_number] => 11914713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Access to firmware settings with asymmetric cryptography [patent_app_type] => utility [patent_app_number] => 17/052991 [patent_app_country] => US [patent_app_date] => 2019-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5033 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17052991 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/052991
Access to firmware settings with asymmetric cryptography Feb 27, 2019 Issued
Array ( [id] => 14719263 [patent_doc_number] => 20190250695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => DYNAMICALLY CHANGING DATA ACCESS BANDWIDTH BY SELECTIVELY ENABLING AND DISABLING DATA LINKS [patent_app_type] => utility [patent_app_number] => 16/272346 [patent_app_country] => US [patent_app_date] => 2019-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19301 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16272346 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/272346
Dynamically changing data access bandwidth by selectively enabling and disabling data links Feb 10, 2019 Issued
Array ( [id] => 17816978 [patent_doc_number] => 11422585 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Clock calibration [patent_app_type] => utility [patent_app_number] => 16/961209 [patent_app_country] => US [patent_app_date] => 2019-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4971 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16961209 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/961209
Clock calibration Jan 13, 2019 Issued
Array ( [id] => 14443031 [patent_doc_number] => 20190179388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => METHOD AND APPARATUS FOR PROVIDING STANDBY POWER TO AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/209809 [patent_app_country] => US [patent_app_date] => 2018-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3159 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16209809 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/209809
Method and apparatus for providing standby power to an integrated circuit Dec 3, 2018 Issued
Array ( [id] => 15836193 [patent_doc_number] => 20200133379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => Method and Apparatus for Extending Power Hold-Up with Power Assist Unit [patent_app_type] => utility [patent_app_number] => 16/175828 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13214 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16175828 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/175828
Method and apparatus for extending power hold-up with power assist unit Oct 29, 2018 Issued
Array ( [id] => 17091363 [patent_doc_number] => 11119549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Machine intelligence performance boost with energy reservoir [patent_app_type] => utility [patent_app_number] => 16/174807 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4020 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16174807 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/174807
Machine intelligence performance boost with energy reservoir Oct 29, 2018 Issued
Array ( [id] => 14934469 [patent_doc_number] => 20190302872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => ELECTRONIC DEVICE HAVING AN ACTIVE EDGE [patent_app_type] => utility [patent_app_number] => 16/175045 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3276 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16175045 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/175045
Electronic device having an active edge Oct 29, 2018 Issued
Array ( [id] => 14378685 [patent_doc_number] => 20190163255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => CORE OFF SLEEP MODE WITH LOW EXIT LATENCY [patent_app_type] => utility [patent_app_number] => 16/175232 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20895 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16175232 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/175232
Core off sleep mode with low exit latency Oct 29, 2018 Issued
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