![](/images/general/no_picture/200_user.png)
William J Levicky
Examiner (ID: 16553, Phone: (571)270-3983 , Office: P/3762 )
Most Active Art Unit | 3762 |
Art Unit(s) | 3762, 3792, 3796 |
Total Applications | 576 |
Issued Applications | 356 |
Pending Applications | 59 |
Abandoned Applications | 161 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 1339010
[patent_doc_number] => 06601120
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[patent_kind] => B1
[patent_issue_date] => 2003-07-29
[patent_title] => 'System, method and computer program product for implementing scalable multi-reader/single-writer locks'
[patent_app_type] => B1
[patent_app_number] => 09/615312
[patent_app_country] => US
[patent_app_date] => 2000-07-13
[patent_effective_date] => 0000-00-00
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[patent_figures_cnt] => 9
[patent_no_of_words] => 5593
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[pdf_file] => patents/06/601/06601120.pdf
[firstpage_image] =>[orig_patent_app_number] => 09615312
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/615312 | System, method and computer program product for implementing scalable multi-reader/single-writer locks | Jul 12, 2000 | Issued |
Array
(
[id] => 1425125
[patent_doc_number] => 06535948
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-03-18
[patent_title] => 'Serial interface unit'
[patent_app_type] => B1
[patent_app_number] => 09/583493
[patent_app_country] => US
[patent_app_date] => 2000-05-31
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 09583493
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/583493 | Serial interface unit | May 30, 2000 | Issued |
Array
(
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[patent_doc_number] => 06584539
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-06-24
[patent_title] => 'Method and system for message broadcast flow control on a bus bridge interconnect'
[patent_app_type] => B1
[patent_app_number] => 09/531278
[patent_app_country] => US
[patent_app_date] => 2000-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/531278 | Method and system for message broadcast flow control on a bus bridge interconnect | Mar 17, 2000 | Issued |
Array
(
[id] => 1409123
[patent_doc_number] => 06557064
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-29
[patent_title] => 'Set up time adjust'
[patent_app_type] => B1
[patent_app_number] => 09/507071
[patent_app_country] => US
[patent_app_date] => 2000-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 4959
[patent_no_of_claims] => 21
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[pdf_file] => patents/06/557/06557064.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/507071 | Set up time adjust | Feb 17, 2000 | Issued |
Array
(
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[patent_doc_number] => 06560664
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[patent_issue_date] => 2003-05-06
[patent_title] => 'Method and apparatus for translation lookaside buffers to access a common hardware page walker'
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[patent_app_number] => 09/507037
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[pdf_file] => patents/06/560/06560664.pdf
[firstpage_image] =>[orig_patent_app_number] => 09507037
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/507037 | Method and apparatus for translation lookaside buffers to access a common hardware page walker | Feb 17, 2000 | Issued |
Array
(
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[patent_doc_number] => 06493785
[patent_country] => US
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[patent_issue_date] => 2002-12-10
[patent_title] => 'Communication mode between SCSI devices'
[patent_app_type] => B1
[patent_app_number] => 09/506709
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Array
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[patent_doc_number] => 06523082
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[patent_issue_date] => 2003-02-18
[patent_title] => 'Systems having shared memory and buses'
[patent_app_type] => B1
[patent_app_number] => 09/506273
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[pdf_file] => patents/06/523/06523082.pdf
[firstpage_image] =>[orig_patent_app_number] => 09506273
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/506273 | Systems having shared memory and buses | Feb 16, 2000 | Issued |
Array
(
[id] => 1420906
[patent_doc_number] => 06542946
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-01
[patent_title] => 'Dual mode differential transceiver for a universal serial bus'
[patent_app_type] => B1
[patent_app_number] => 09/493322
[patent_app_country] => US
[patent_app_date] => 2000-01-28
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/542/06542946.pdf
[firstpage_image] =>[orig_patent_app_number] => 09493322
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/493322 | Dual mode differential transceiver for a universal serial bus | Jan 27, 2000 | Issued |
Array
(
[id] => 1411347
[patent_doc_number] => 06553447
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-22
[patent_title] => 'Data processing system with fully interconnected system architecture (FISA)'
[patent_app_type] => B1
[patent_app_number] => 09/437194
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[patent_app_date] => 1999-11-09
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[pdf_file] => patents/06/553/06553447.pdf
[firstpage_image] =>[orig_patent_app_number] => 09437194
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/437194 | Data processing system with fully interconnected system architecture (FISA) | Nov 8, 1999 | Issued |
Array
(
[id] => 1406392
[patent_doc_number] => 06560663
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-06
[patent_title] => 'Method and system for controlling internal busses to prevent bus contention during internal scan testing'
[patent_app_type] => B1
[patent_app_number] => 09/389873
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[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[patent_no_of_words] => 6651
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[pdf_file] => patents/06/560/06560663.pdf
[firstpage_image] =>[orig_patent_app_number] => 09389873
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/389873 | Method and system for controlling internal busses to prevent bus contention during internal scan testing | Sep 1, 1999 | Issued |
Array
(
[id] => 1431086
[patent_doc_number] => 06523075
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-18
[patent_title] => 'Method and system for controlling internal busses to prevent busses contention during internal scan testing by using a centralized control resource'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/389871 | Method and system for controlling internal busses to prevent busses contention during internal scan testing by using a centralized control resource | Sep 1, 1999 | Issued |