William J. Royer

Array ( [id] => 20009667 [patent_doc_number] => 20250147889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => SYSTEMS AND METHODS FOR CACHE WARMING IN A DISTRIBUTED DATA STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 18/501692 [patent_app_country] => US [patent_app_date] => 2023-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5064 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18501692 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20000793 [patent_doc_number] => 20250139015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => LOW WATERMARK BUFFER CACHE [patent_app_type] => utility [patent_app_number] => 18/495478 [patent_app_country] => US [patent_app_date] => 2023-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2609 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18495478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18957395 [patent_doc_number] => 20240045722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => ACCELERATING TABLE LOOKUPS USING A DECOUPLED LOOKUP TABLE ACCELERATOR IN A SYSTEM ON A CHIP [patent_app_type] => utility [patent_app_number] => 18/488674 [patent_app_country] => US [patent_app_date] => 2023-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 58437 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18488674 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19099773 [patent_doc_number] => 20240119001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => METHOD FOR CACHING AND MIGRATING DE-COMPRESSED PAGE [patent_app_type] => utility [patent_app_number] => 18/377597 [patent_app_country] => US [patent_app_date] => 2023-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7497 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18377597 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20257729 [patent_doc_number] => 12430079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Low-latency code fetching from memory [patent_app_type] => utility [patent_app_number] => 18/477450 [patent_app_country] => US [patent_app_date] => 2023-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3330 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18477450 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19864693 [patent_doc_number] => 20250103479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => Dynamic Random-Access Memory (DRAM) Efficiency Calculation and Utilization of Last Level Cache (LLC) [patent_app_type] => utility [patent_app_number] => 18/475492 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10572 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18475492 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19848991 [patent_doc_number] => 20250094342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => DESIGN VERIFICATION PROCESS FOR BIT SPREADING ERROR RESISTANT MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/470111 [patent_app_country] => US [patent_app_date] => 2023-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9291 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18470111 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19818902 [patent_doc_number] => 20250077109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => ERASE VERIFICATION FOR A NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/460041 [patent_app_country] => US [patent_app_date] => 2023-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7569 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18460041 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19204618 [patent_doc_number] => 20240176517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => FLASH MEMORY CONTROLLER THAT CAN QUICKLY ENTER POWER SAVING MODE AFTER ENTERING IDLE STATE, ASSOCIATED FLASH MEMORY DEVICE, AND ASSOCIATED CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 18/220240 [patent_app_country] => US [patent_app_date] => 2023-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3451 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18220240 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19544875 [patent_doc_number] => 20240361911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => Statistically Driven Run Level Firmware Migration [patent_app_type] => utility [patent_app_number] => 18/218876 [patent_app_country] => US [patent_app_date] => 2023-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6336 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18218876 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18728020 [patent_doc_number] => 20230342313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => Systems And Methods For Load Balancing Memory Traffic [patent_app_type] => utility [patent_app_number] => 18/215732 [patent_app_country] => US [patent_app_date] => 2023-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5785 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18215732 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19660832 [patent_doc_number] => 20240427897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => Secure stacking of memory dies [patent_app_type] => utility [patent_app_number] => 18/339249 [patent_app_country] => US [patent_app_date] => 2023-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7109 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18339249 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19645076 [patent_doc_number] => 20240419596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => CACHING STRATEGY DETERMINATION AND INJECTION [patent_app_type] => utility [patent_app_number] => 18/335351 [patent_app_country] => US [patent_app_date] => 2023-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4646 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18335351 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19552284 [patent_doc_number] => 12135993 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-05 [patent_title] => Hybrid memory in a dynamically power gated hardware accelerator [patent_app_type] => utility [patent_app_number] => 18/321919 [patent_app_country] => US [patent_app_date] => 2023-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 11937 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18321919 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19719233 [patent_doc_number] => 12204772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Memory devices and methods for managing use history [patent_app_type] => utility [patent_app_number] => 18/195587 [patent_app_country] => US [patent_app_date] => 2023-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10395 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18195587 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19573862 [patent_doc_number] => 20240378154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => OPERATIONS IN A PROCESSOR CACHE BASED ON OCCUPANCY STATE [patent_app_type] => utility [patent_app_number] => 18/314495 [patent_app_country] => US [patent_app_date] => 2023-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16541 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314495 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19174601 [patent_doc_number] => 20240160575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => STORAGE DEVICE FOR LOAD BALANCING AND METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 18/312349 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8609 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312349 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19925021 [patent_doc_number] => 12299303 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Dynamic reserve capacity in storage systems [patent_app_type] => utility [patent_app_number] => 18/138415 [patent_app_country] => US [patent_app_date] => 2023-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6097 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18138415 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19144310 [patent_doc_number] => 20240143222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => STORAGE DEVICE CONTROLLING WRITE BUFFER WHILE PROCESSING POWER OFF REQUEST AND METHOD OF OPERATING THE STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/301781 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7736 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18301781 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19114702 [patent_doc_number] => 20240126452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => STORAGE DEVICE AND OPERATING METHOD OF CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/184547 [patent_app_country] => US [patent_app_date] => 2023-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3636 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18184547 [rel_patent_id] =>[rel_patent_doc_number] =>)