Search

William K. Cheung

Examiner (ID: 10583)

Most Active Art Unit
1762
Art Unit(s)
1762, 1713, 1796
Total Applications
2398
Issued Applications
1935
Pending Applications
41
Abandoned Applications
433

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4847782 [patent_doc_number] => 20080184190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'METHOD FOR RESIZING PATTERN TO BE WRITTEN BY LITHOGRAPHY TECHNIQUE, AND CHARGED PARTICLE BEAM WRITING METHOD' [patent_app_type] => utility [patent_app_number] => 11/851176 [patent_app_country] => US [patent_app_date] => 2007-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6904 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20080184190.pdf [firstpage_image] =>[orig_patent_app_number] => 11851176 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/851176
Method for resizing pattern to be written by lithography technique, and charged particle beam writing method Sep 5, 2007 Issued
Array ( [id] => 146846 [patent_doc_number] => 07689942 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-30 [patent_title] => 'Simultaneous power and timing optimization in integrated circuits by performing discrete actions on circuit components' [patent_app_type] => utility [patent_app_number] => 11/845056 [patent_app_country] => US [patent_app_date] => 2007-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8495 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/689/07689942.pdf [firstpage_image] =>[orig_patent_app_number] => 11845056 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/845056
Simultaneous power and timing optimization in integrated circuits by performing discrete actions on circuit components Aug 24, 2007 Issued
Array ( [id] => 4671788 [patent_doc_number] => 20080046849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'METHOD FOR CHANGING PHYSICAL LAYOUT DATA USING VIRTUAL LAYER' [patent_app_type] => utility [patent_app_number] => 11/839206 [patent_app_country] => US [patent_app_date] => 2007-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2625 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20080046849.pdf [firstpage_image] =>[orig_patent_app_number] => 11839206 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/839206
METHOD FOR CHANGING PHYSICAL LAYOUT DATA USING VIRTUAL LAYER Aug 14, 2007 Abandoned
Array ( [id] => 4587386 [patent_doc_number] => 07849436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Method of forming dummy pattern' [patent_app_type] => utility [patent_app_number] => 11/889384 [patent_app_country] => US [patent_app_date] => 2007-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2571 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/849/07849436.pdf [firstpage_image] =>[orig_patent_app_number] => 11889384 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/889384
Method of forming dummy pattern Aug 12, 2007 Issued
Array ( [id] => 4690155 [patent_doc_number] => 20080034336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'Electro-migration verifying apparatus, electro-migration verifying method, data structure and netlist used in the same' [patent_app_type] => utility [patent_app_number] => 11/882344 [patent_app_country] => US [patent_app_date] => 2007-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8099 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20080034336.pdf [firstpage_image] =>[orig_patent_app_number] => 11882344 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/882344
Electro-migration verifying apparatus, electro-migration verifying method, data structure and netlist used in the same Jul 31, 2007 Issued
Array ( [id] => 69198 [patent_doc_number] => 07761818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-20 [patent_title] => 'Obtaining a feasible integer solution in a hierarchical circuit layout optimization' [patent_app_type] => utility [patent_app_number] => 11/782706 [patent_app_country] => US [patent_app_date] => 2007-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 6440 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/761/07761818.pdf [firstpage_image] =>[orig_patent_app_number] => 11782706 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/782706
Obtaining a feasible integer solution in a hierarchical circuit layout optimization Jul 24, 2007 Issued
Array ( [id] => 4659481 [patent_doc_number] => 20080028343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF DESIGNING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/779366 [patent_app_country] => US [patent_app_date] => 2007-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6182 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20080028343.pdf [firstpage_image] =>[orig_patent_app_number] => 11779366 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/779366
SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF DESIGNING THE SAME Jul 17, 2007 Abandoned
Array ( [id] => 156349 [patent_doc_number] => 07681152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-16 [patent_title] => 'Design structures comprising voltage translator circuits' [patent_app_type] => utility [patent_app_number] => 11/778106 [patent_app_country] => US [patent_app_date] => 2007-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3710 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/681/07681152.pdf [firstpage_image] =>[orig_patent_app_number] => 11778106 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/778106
Design structures comprising voltage translator circuits Jul 15, 2007 Issued
Array ( [id] => 5351672 [patent_doc_number] => 20090007033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'Method to transfer failure analysis-specific data between data between design houses and fab\'s/FA labs' [patent_app_type] => utility [patent_app_number] => 11/823566 [patent_app_country] => US [patent_app_date] => 2007-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3534 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20090007033.pdf [firstpage_image] =>[orig_patent_app_number] => 11823566 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/823566
Method to transfer failure analysis-specific data between data between design houses and fab's/FA labs Jun 27, 2007 Abandoned
Array ( [id] => 37843 [patent_doc_number] => 07793247 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-09-07 [patent_title] => 'Method and apparatus for directed physical implementation of a circuit design for an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/818012 [patent_app_country] => US [patent_app_date] => 2007-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5568 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/793/07793247.pdf [firstpage_image] =>[orig_patent_app_number] => 11818012 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/818012
Method and apparatus for directed physical implementation of a circuit design for an integrated circuit Jun 12, 2007 Issued
Array ( [id] => 7683917 [patent_doc_number] => 20100122224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'METHOD AND APPARATUS FOR DESIGNING AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/597034 [patent_app_country] => US [patent_app_date] => 2007-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1952 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20100122224.pdf [firstpage_image] =>[orig_patent_app_number] => 12597034 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/597034
METHOD AND APPARATUS FOR DESIGNING AN INTEGRATED CIRCUIT May 2, 2007 Abandoned
Array ( [id] => 4940572 [patent_doc_number] => 20080077892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'Circuit unit designing apparatus, circuit unit designing method, and circuit unit designing program' [patent_app_type] => utility [patent_app_number] => 11/790666 [patent_app_country] => US [patent_app_date] => 2007-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7042 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20080077892.pdf [firstpage_image] =>[orig_patent_app_number] => 11790666 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/790666
Circuit unit designing apparatus, circuit unit designing method, and circuit unit designing program Apr 25, 2007 Abandoned
Array ( [id] => 5127822 [patent_doc_number] => 20070240093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'Architecture and method for providing integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/787206 [patent_app_country] => US [patent_app_date] => 2007-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 5785 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20070240093.pdf [firstpage_image] =>[orig_patent_app_number] => 11787206 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/787206
Architecture and method for providing integrated circuits Apr 9, 2007 Abandoned
Array ( [id] => 17604 [patent_doc_number] => 07805689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-28 [patent_title] => 'Circuit board information acquisition and conversion method, program, and device for the same' [patent_app_type] => utility [patent_app_number] => 11/675304 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8081 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/805/07805689.pdf [firstpage_image] =>[orig_patent_app_number] => 11675304 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/675304
Circuit board information acquisition and conversion method, program, and device for the same Feb 14, 2007 Issued
Array ( [id] => 136701 [patent_doc_number] => 07703053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-20 [patent_title] => 'Regional pattern density determination method and system' [patent_app_type] => utility [patent_app_number] => 11/566884 [patent_app_country] => US [patent_app_date] => 2006-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2732 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/703/07703053.pdf [firstpage_image] =>[orig_patent_app_number] => 11566884 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/566884
Regional pattern density determination method and system Dec 4, 2006 Issued
Array ( [id] => 4693938 [patent_doc_number] => 20080086709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'System and method for automatic elimination of electromigration and self heat violations during construction of a mask layout block, maintaining the process design rules (DRC Clean) and layout connectivity (LVS Clean) correctness' [patent_app_type] => utility [patent_app_number] => 11/542910 [patent_app_country] => US [patent_app_date] => 2006-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3492 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20080086709.pdf [firstpage_image] =>[orig_patent_app_number] => 11542910 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/542910
System and method for automatic elimination of electromigration and self heat violations during construction of a mask layout block, maintaining the process design rules (DRC Clean) and layout connectivity (LVS Clean) correctness Oct 4, 2006 Abandoned
Array ( [id] => 4693937 [patent_doc_number] => 20080086708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'System and method for automatic elimination of electromigration and self heat violations of a mask layout block, maintaining the process design rules correctness' [patent_app_type] => utility [patent_app_number] => 11/542909 [patent_app_country] => US [patent_app_date] => 2006-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2978 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20080086708.pdf [firstpage_image] =>[orig_patent_app_number] => 11542909 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/542909
System and method for automatic elimination of electromigration and self heat violations of a mask layout block, maintaining the process design rules correctness Oct 4, 2006 Abandoned
Array ( [id] => 5053020 [patent_doc_number] => 20070033565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-08 [patent_title] => 'Basic cell of semiconductor integrated circuit and layout method thereof' [patent_app_type] => utility [patent_app_number] => 11/497243 [patent_app_country] => US [patent_app_date] => 2006-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4444 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20070033565.pdf [firstpage_image] =>[orig_patent_app_number] => 11497243 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/497243
Basic cell of semiconductor integrated circuit and layout method thereof Aug 1, 2006 Abandoned
Array ( [id] => 4577981 [patent_doc_number] => 07823096 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-26 [patent_title] => 'Inductance analysis system and method and program therefor' [patent_app_type] => utility [patent_app_number] => 11/495711 [patent_app_country] => US [patent_app_date] => 2006-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4574 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/823/07823096.pdf [firstpage_image] =>[orig_patent_app_number] => 11495711 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/495711
Inductance analysis system and method and program therefor Jul 30, 2006 Issued
Array ( [id] => 4659497 [patent_doc_number] => 20080028359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'Termination structure, a mask for manufacturing a termination structure, a lithographic process and a semiconductor device with a termination structure' [patent_app_type] => utility [patent_app_number] => 11/496279 [patent_app_country] => US [patent_app_date] => 2006-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3709 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20080028359.pdf [firstpage_image] =>[orig_patent_app_number] => 11496279 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/496279
Termination structure, a mask for manufacturing a termination structure, a lithographic process and a semiconductor device with a termination structure Jul 30, 2006 Abandoned
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