| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_issue_date] => 2008-07-31
[patent_title] => 'METHOD FOR RESIZING PATTERN TO BE WRITTEN BY LITHOGRAPHY TECHNIQUE, AND CHARGED PARTICLE BEAM WRITING METHOD'
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Array
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[patent_doc_number] => 07689942
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-30
[patent_title] => 'Simultaneous power and timing optimization in integrated circuits by performing discrete actions on circuit components'
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[patent_app_number] => 11/845056
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/845056 | Simultaneous power and timing optimization in integrated circuits by performing discrete actions on circuit components | Aug 24, 2007 | Issued |
Array
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[patent_doc_number] => 20080046849
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-21
[patent_title] => 'METHOD FOR CHANGING PHYSICAL LAYOUT DATA USING VIRTUAL LAYER'
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[patent_app_number] => 11/839206
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Array
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[patent_doc_number] => 07849436
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[patent_kind] => B2
[patent_issue_date] => 2010-12-07
[patent_title] => 'Method of forming dummy pattern'
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[patent_app_number] => 11/889384
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[patent_app_date] => 2007-08-13
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[patent_kind] => A1
[patent_issue_date] => 2008-02-07
[patent_title] => 'Electro-migration verifying apparatus, electro-migration verifying method, data structure and netlist used in the same'
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[patent_app_number] => 11/882344
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Array
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[patent_kind] => A1
[patent_issue_date] => 2008-01-31
[patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF DESIGNING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/779366
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[patent_app_date] => 2007-07-18
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/779366 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF DESIGNING THE SAME | Jul 17, 2007 | Abandoned |
Array
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[patent_doc_number] => 07681152
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[patent_kind] => B2
[patent_issue_date] => 2010-03-16
[patent_title] => 'Design structures comprising voltage translator circuits'
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[patent_app_number] => 11/778106
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[firstpage_image] =>[orig_patent_app_number] => 11778106
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/778106 | Design structures comprising voltage translator circuits | Jul 15, 2007 | Issued |
Array
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[patent_doc_number] => 20090007033
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[patent_kind] => A1
[patent_issue_date] => 2009-01-01
[patent_title] => 'Method to transfer failure analysis-specific data between data between design houses and fab\'s/FA labs'
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[patent_app_number] => 11/823566
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/823566 | Method to transfer failure analysis-specific data between data between design houses and fab's/FA labs | Jun 27, 2007 | Abandoned |
Array
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[id] => 37843
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[patent_kind] => B1
[patent_issue_date] => 2010-09-07
[patent_title] => 'Method and apparatus for directed physical implementation of a circuit design for an integrated circuit'
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[patent_app_number] => 11/818012
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Array
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[id] => 7683917
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[patent_issue_date] => 2010-05-13
[patent_title] => 'METHOD AND APPARATUS FOR DESIGNING AN INTEGRATED CIRCUIT'
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[patent_app_number] => 12/597034
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Array
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Array
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