
William L. Bashore
Supervisory Patent Examiner (ID: 4398, Phone: (571)272-4088 , Office: P/2175 )
| Most Active Art Unit | 2176 |
| Art Unit(s) | 2176, 2174, 2776, 2175, 2777 |
| Total Applications | 363 |
| Issued Applications | 182 |
| Pending Applications | 73 |
| Abandoned Applications | 111 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17948980
[patent_doc_number] => 20220335999
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-20
[patent_title] => FORCED CURRENT ACCESS WITH VOLTAGE CLAMPING IN CROSS-POINT ARRAY
[patent_app_type] => utility
[patent_app_number] => 17/846684
[patent_app_country] => US
[patent_app_date] => 2022-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 21758
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17846684
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/846684 | Forced current access with voltage clamping in cross-point array | Jun 21, 2022 | Issued |
Array
(
[id] => 18820838
[patent_doc_number] => 20230395179
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-07
[patent_title] => INTERRUPTING A MEMORY BUILT-IN SELF-TEST
[patent_app_type] => utility
[patent_app_number] => 17/808043
[patent_app_country] => US
[patent_app_date] => 2022-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17367
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17808043
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/808043 | Interrupting a memory built-in self-test | Jun 20, 2022 | Issued |
Array
(
[id] => 18688127
[patent_doc_number] => 11783870
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-10
[patent_title] => Sense amplifier
[patent_app_type] => utility
[patent_app_number] => 17/843786
[patent_app_country] => US
[patent_app_date] => 2022-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 11706
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17843786
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/843786 | Sense amplifier | Jun 16, 2022 | Issued |
Array
(
[id] => 18890830
[patent_doc_number] => 11869607
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-09
[patent_title] => Memory location age tracking on memory die
[patent_app_type] => utility
[patent_app_number] => 17/838873
[patent_app_country] => US
[patent_app_date] => 2022-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 11930
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17838873
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/838873 | Memory location age tracking on memory die | Jun 12, 2022 | Issued |
Array
(
[id] => 19414500
[patent_doc_number] => 12080332
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-03
[patent_title] => Memory device, a memory system having the same and an operating method thereof in which a row address is not separated depending on pages in a byte mode operation
[patent_app_type] => utility
[patent_app_number] => 17/834320
[patent_app_country] => US
[patent_app_date] => 2022-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 21
[patent_no_of_words] => 7751
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17834320
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/834320 | Memory device, a memory system having the same and an operating method thereof in which a row address is not separated depending on pages in a byte mode operation | Jun 6, 2022 | Issued |
Array
(
[id] => 18455860
[patent_doc_number] => 20230197141
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-22
[patent_title] => MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/834516
[patent_app_country] => US
[patent_app_date] => 2022-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10543
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17834516
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/834516 | Memory device | Jun 6, 2022 | Issued |
Array
(
[id] => 19414523
[patent_doc_number] => 12080357
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-03
[patent_title] => Memory device and operating method using application of pass voltage according to program loops
[patent_app_type] => utility
[patent_app_number] => 17/833114
[patent_app_country] => US
[patent_app_date] => 2022-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 21
[patent_no_of_words] => 13334
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17833114
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/833114 | Memory device and operating method using application of pass voltage according to program loops | Jun 5, 2022 | Issued |
Array
(
[id] => 18823173
[patent_doc_number] => 20230397514
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-07
[patent_title] => TUNABLE RESISTIVE RANDOM ACCESS MEMORY CELL
[patent_app_type] => utility
[patent_app_number] => 17/804912
[patent_app_country] => US
[patent_app_date] => 2022-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4220
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 39
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17804912
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/804912 | Tunable resistive random access memory cell | May 31, 2022 | Issued |
Array
(
[id] => 19313371
[patent_doc_number] => 12039185
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-16
[patent_title] => Controller for storing performance information based on test operation result, operating method thereof and computing system including the same
[patent_app_type] => utility
[patent_app_number] => 17/749235
[patent_app_country] => US
[patent_app_date] => 2022-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 31
[patent_no_of_words] => 19017
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17749235
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/749235 | Controller for storing performance information based on test operation result, operating method thereof and computing system including the same | May 19, 2022 | Issued |
Array
(
[id] => 18874397
[patent_doc_number] => 11862218
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-02
[patent_title] => Read circuit for magnetic tunnel junction (MTJ) memory
[patent_app_type] => utility
[patent_app_number] => 17/748560
[patent_app_country] => US
[patent_app_date] => 2022-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 7362
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17748560
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/748560 | Read circuit for magnetic tunnel junction (MTJ) memory | May 18, 2022 | Issued |
Array
(
[id] => 18865576
[patent_doc_number] => 20230420013
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-28
[patent_title] => METHOD OF STORING DATA IN MEMORIES
[patent_app_type] => utility
[patent_app_number] => 17/747318
[patent_app_country] => US
[patent_app_date] => 2022-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11807
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747318
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/747318 | Method of storing data in memories | May 17, 2022 | Issued |
Array
(
[id] => 18735519
[patent_doc_number] => 11804260
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-31
[patent_title] => Multiplexors under an array of memory cells
[patent_app_type] => utility
[patent_app_number] => 17/746542
[patent_app_country] => US
[patent_app_date] => 2022-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7221
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17746542
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/746542 | Multiplexors under an array of memory cells | May 16, 2022 | Issued |
Array
(
[id] => 18439694
[patent_doc_number] => 20230186989
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-15
[patent_title] => MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/746375
[patent_app_country] => US
[patent_app_date] => 2022-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10170
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17746375
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/746375 | Memory device storing logical page data and operating method of the memory device | May 16, 2022 | Issued |
Array
(
[id] => 19277070
[patent_doc_number] => 12027201
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-02
[patent_title] => Column select signal cell circuit, bit line sense circuit and memory
[patent_app_type] => utility
[patent_app_number] => 17/743497
[patent_app_country] => US
[patent_app_date] => 2022-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 9797
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17743497
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/743497 | Column select signal cell circuit, bit line sense circuit and memory | May 12, 2022 | Issued |
Array
(
[id] => 18757223
[patent_doc_number] => 20230360681
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-09
[patent_title] => PULSE BASED MULTI-LEVEL CELL PROGRAMMING
[patent_app_type] => utility
[patent_app_number] => 17/740069
[patent_app_country] => US
[patent_app_date] => 2022-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16305
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17740069
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/740069 | Pulse based multi-level cell programming | May 8, 2022 | Issued |
Array
(
[id] => 17810617
[patent_doc_number] => 20220262452
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-18
[patent_title] => MEMORY DEVICE AND MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 17/735860
[patent_app_country] => US
[patent_app_date] => 2022-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19917
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17735860
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/735860 | Memory device and memory system capable of using redundancy memory cells | May 2, 2022 | Issued |
Array
(
[id] => 17810608
[patent_doc_number] => 20220262443
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-18
[patent_title] => SEMICONDUCTOR MEMORY WITH DIFFERENT THRESHOLD VOLTAGES OF MEMORY CELLS
[patent_app_type] => utility
[patent_app_number] => 17/735196
[patent_app_country] => US
[patent_app_date] => 2022-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 94759
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17735196
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/735196 | Semiconductor memory with different threshold voltages of memory cells | May 2, 2022 | Issued |
Array
(
[id] => 17810619
[patent_doc_number] => 20220262454
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-18
[patent_title] => MEMORY DEVICE AND MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 17/735889
[patent_app_country] => US
[patent_app_date] => 2022-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19921
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -3
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17735889
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/735889 | Memory device for selectively operating multiple memory groups in different speeds and memory system including the same | May 2, 2022 | Issued |
Array
(
[id] => 17810618
[patent_doc_number] => 20220262453
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-18
[patent_title] => MEMORY DEVICE AND MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 17/735881
[patent_app_country] => US
[patent_app_date] => 2022-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19917
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -2
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17735881
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/735881 | Memory device for selectively operating multiple memory groups in different speeds and memory system including the same | May 2, 2022 | Issued |
Array
(
[id] => 18729077
[patent_doc_number] => 20230343372
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-26
[patent_title] => AREA-EFFICIENT CONFIGURATION LATCH FOR PROGRAMMABLE LOGIC DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/725564
[patent_app_country] => US
[patent_app_date] => 2022-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12620
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 378
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17725564
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/725564 | Area-efficient configuration latch for programmable logic device | Apr 20, 2022 | Issued |