Search

William L. Miller

Examiner (ID: 7380, Phone: (571)272-7068 , Office: P/3677 )

Most Active Art Unit
3677
Art Unit(s)
3628, 3677, 3509, 3633
Total Applications
3236
Issued Applications
2469
Pending Applications
164
Abandoned Applications
642

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11732997 [patent_doc_number] => 20170194440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/892318 [patent_app_country] => US [patent_app_date] => 2015-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4220 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14892318 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/892318
Thin film transistor, manufacturing method thereof, and display device including the same Oct 25, 2015 Issued
Array ( [id] => 10652232 [patent_doc_number] => 09368498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-14 [patent_title] => 'FinFET device with dual-strained channels and method for manufacturing thereof' [patent_app_type] => utility [patent_app_number] => 14/878012 [patent_app_country] => US [patent_app_date] => 2015-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 10683 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14878012 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/878012
FinFET device with dual-strained channels and method for manufacturing thereof Oct 7, 2015 Issued
Array ( [id] => 11532642 [patent_doc_number] => 20170092619 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'STACKED SILICON PACKAGE ASSEMBLY HAVING AN ENHANCED LID' [patent_app_type] => utility [patent_app_number] => 14/867349 [patent_app_country] => US [patent_app_date] => 2015-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9980 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14867349 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/867349
Stacked silicon package assembly having an enhanced lid Sep 27, 2015 Issued
Array ( [id] => 10780987 [patent_doc_number] => 20160127143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-05 [patent_title] => 'APPARATUS AND METHOD FOR MANAGING DEVICES' [patent_app_type] => utility [patent_app_number] => 14/827921 [patent_app_country] => US [patent_app_date] => 2015-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 16697 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14827921 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/827921
Apparatus and method for managing devices Aug 16, 2015 Issued
Array ( [id] => 11664803 [patent_doc_number] => 20170153522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'BASEPLATE CIRCUIT AND DISPLAY PANEL' [patent_app_type] => utility [patent_app_number] => 14/773355 [patent_app_country] => US [patent_app_date] => 2015-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3026 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14773355 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/773355
Baseplate circuit and display panel Aug 10, 2015 Issued
Array ( [id] => 11446250 [patent_doc_number] => 20170047271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'METHOD FOR MAKING A SEMICONDUCTOR DEVICE HAVING AN INTERPOSER' [patent_app_type] => utility [patent_app_number] => 14/821974 [patent_app_country] => US [patent_app_date] => 2015-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3661 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14821974 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/821974
METHOD FOR MAKING A SEMICONDUCTOR DEVICE HAVING AN INTERPOSER Aug 9, 2015 Abandoned
Array ( [id] => 10672318 [patent_doc_number] => 20160018463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-21 [patent_title] => 'SIGNAL PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/802484 [patent_app_country] => US [patent_app_date] => 2015-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6550 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14802484 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/802484
Signal processing apparatus Jul 16, 2015 Issued
Array ( [id] => 10816221 [patent_doc_number] => 20160162382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'SYSTEM THAT COMPARES DATA CENTER EQUIPMENT ABNORMALITIES TO SLAS AND AUTOMATICALLY COMMUNICATES CRITICAL INFORMATION TO INTERESTED PARTIES FOR RESPONSE' [patent_app_type] => utility [patent_app_number] => 14/802356 [patent_app_country] => US [patent_app_date] => 2015-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3831 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14802356 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/802356
SYSTEM THAT COMPARES DATA CENTER EQUIPMENT ABNORMALITIES TO SLAS AND AUTOMATICALLY COMMUNICATES CRITICAL INFORMATION TO INTERESTED PARTIES FOR RESPONSE Jul 16, 2015 Abandoned
Array ( [id] => 12294045 [patent_doc_number] => 09935036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-03 [patent_title] => Package assembly with gathered insulated wires [patent_app_type] => utility [patent_app_number] => 15/036385 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 10630 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15036385 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/036385
Package assembly with gathered insulated wires Jun 25, 2015 Issued
Array ( [id] => 12376146 [patent_doc_number] => 09960276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-01 [patent_title] => ESL TFT substrate structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 14/764169 [patent_app_country] => US [patent_app_date] => 2015-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4041 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14764169 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/764169
ESL TFT substrate structure and manufacturing method thereof Jun 22, 2015 Issued
Array ( [id] => 11652916 [patent_doc_number] => 20170148817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'METHOD FOR MANUFACTURING TFT SUBSTRATE AND STRUCTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 14/759190 [patent_app_country] => US [patent_app_date] => 2015-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5042 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14759190 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/759190
Method for manufacturing TFT substrate and structure thereof May 26, 2015 Issued
Array ( [id] => 10452134 [patent_doc_number] => 20150337148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'PRINTABLE COMPOSITIONS USEFUL IN ELECTRONIC APPLICATIONS AND METHODS RELATING THERETO' [patent_app_type] => utility [patent_app_number] => 14/719630 [patent_app_country] => US [patent_app_date] => 2015-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3250 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14719630 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/719630
Printable compositions useful in electronic applications and methods relating thereto May 21, 2015 Issued
Array ( [id] => 10455491 [patent_doc_number] => 20150340505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/719431 [patent_app_country] => US [patent_app_date] => 2015-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 52 [patent_no_of_words] => 48116 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14719431 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/719431
Manufacturing method of semiconductor device May 21, 2015 Issued
Array ( [id] => 10453261 [patent_doc_number] => 20150338276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'CALIBRATION CURVE FORMATION METHOD, IMPURITY CONCENTRATION MEASUREMENT METHOD, AND SEMICONDUCTOR WAFER MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 14/719771 [patent_app_country] => US [patent_app_date] => 2015-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 6742 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14719771 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/719771
Calibration curve formation method, impurity concentration measurement method, and semiconductor wafer manufacturing method May 21, 2015 Issued
Array ( [id] => 11431992 [patent_doc_number] => 09570316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-14 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/718293 [patent_app_country] => US [patent_app_date] => 2015-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 10078 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14718293 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/718293
Method of manufacturing semiconductor device May 20, 2015 Issued
Array ( [id] => 10370411 [patent_doc_number] => 20150255417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'FACILITATING CHIP DICING FOR METAL-METAL BONDING AND HYBRID WAFER BONDING' [patent_app_type] => utility [patent_app_number] => 14/716959 [patent_app_country] => US [patent_app_date] => 2015-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2505 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14716959 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/716959
FACILITATING CHIP DICING FOR METAL-METAL BONDING AND HYBRID WAFER BONDING May 19, 2015 Abandoned
Array ( [id] => 10364015 [patent_doc_number] => 20150249020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-03 [patent_title] => 'SEMICONDUCTOR DEVICE WITH METAL CARRIER AND MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 14/711198 [patent_app_country] => US [patent_app_date] => 2015-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5133 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14711198 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/711198
Semiconductor device with metal carrier and manufacturing method May 12, 2015 Issued
Array ( [id] => 10440478 [patent_doc_number] => 20150325490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'APPARATUS FOR AND METHOD OF PROCESSING SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 14/709775 [patent_app_country] => US [patent_app_date] => 2015-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10799 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14709775 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/709775
Apparatus for and method of processing substrate May 11, 2015 Issued
Array ( [id] => 10329230 [patent_doc_number] => 20150214234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/681934 [patent_app_country] => US [patent_app_date] => 2015-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4030 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14681934 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/681934
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME Apr 7, 2015 Abandoned
Array ( [id] => 11585989 [patent_doc_number] => 09640643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-02 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/678797 [patent_app_country] => US [patent_app_date] => 2015-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 23 [patent_no_of_words] => 4739 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14678797 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/678797
Semiconductor device Apr 2, 2015 Issued
Menu