| Application number | Title of the application | Filing Date | Status |
|---|
| 06/817707 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION | Jan 9, 1986 | Abandoned |
Array
(
[id] => 2306674
[patent_doc_number] => 04673969
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-06-16
[patent_title] => 'Semiconductor device having multiple conductive layers and the method of manufacturing the semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 6/814295
[patent_app_country] => US
[patent_app_date] => 1985-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 16
[patent_no_of_words] => 3559
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/673/04673969.pdf
[firstpage_image] =>[orig_patent_app_number] => 814295
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/814295 | Semiconductor device having multiple conductive layers and the method of manufacturing the semiconductor device | Dec 29, 1985 | Issued |
| 06/807831 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE | Dec 10, 1985 | Issued |
Array
(
[id] => 2394789
[patent_doc_number] => 04777517
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-10-11
[patent_title] => 'Compound semiconductor integrated circuit device'
[patent_app_type] => 1
[patent_app_number] => 6/801782
[patent_app_country] => US
[patent_app_date] => 1985-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 24
[patent_no_of_words] => 5646
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/777/04777517.pdf
[firstpage_image] =>[orig_patent_app_number] => 801782
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/801782 | Compound semiconductor integrated circuit device | Nov 25, 1985 | Issued |
Array
(
[id] => 2294803
[patent_doc_number] => 04679170
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-07-07
[patent_title] => 'Resistor with low thermal activation energy'
[patent_app_type] => 1
[patent_app_number] => 6/797050
[patent_app_country] => US
[patent_app_date] => 1985-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 12
[patent_no_of_words] => 3498
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/679/04679170.pdf
[firstpage_image] =>[orig_patent_app_number] => 797050
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/797050 | Resistor with low thermal activation energy | Nov 11, 1985 | Issued |
Array
(
[id] => 2419968
[patent_doc_number] => 04786956
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-11-22
[patent_title] => 'Input protection device for integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 6/786899
[patent_app_country] => US
[patent_app_date] => 1985-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 6008
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/786/04786956.pdf
[firstpage_image] =>[orig_patent_app_number] => 786899
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/786899 | Input protection device for integrated circuits | Oct 10, 1985 | Issued |
| 06/780504 | METHOD FOR MAKING A HIGH PERFORMANCE TRANSISTOR INTEGRATED CIRCUIT AND THE RESULTING INTEGRATED CIRCUIT | Sep 25, 1985 | Abandoned |
Array
(
[id] => 2456266
[patent_doc_number] => 04768076
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-08-30
[patent_title] => 'Recrystallized CMOS with different crystal planes'
[patent_app_type] => 1
[patent_app_number] => 6/774705
[patent_app_country] => US
[patent_app_date] => 1985-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 16
[patent_no_of_words] => 3481
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 27
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/768/04768076.pdf
[firstpage_image] =>[orig_patent_app_number] => 774705
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/774705 | Recrystallized CMOS with different crystal planes | Sep 10, 1985 | Issued |
| 06/769146 | INTEGRATED CIRCUIT WITH STACKED MOS FIELD EFFECT TRANSISTORS AND METHODS OF MAKING THE SAME | Aug 25, 1985 | Abandoned |
| 06/758885 | HIGH-PERFORMANCE DRAM ARRAYS INCLUDING TRENCH CAPACITORS | Jul 24, 1985 | Abandoned |
Array
(
[id] => 2340196
[patent_doc_number] => 04712122
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-12-08
[patent_title] => 'Heterojunction gate ballistic JFET with channel thinner than Debye length'
[patent_app_type] => 1
[patent_app_number] => 6/759090
[patent_app_country] => US
[patent_app_date] => 1985-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 4505
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/712/04712122.pdf
[firstpage_image] =>[orig_patent_app_number] => 759090
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/759090 | Heterojunction gate ballistic JFET with channel thinner than Debye length | Jul 24, 1985 | Issued |
Array
(
[id] => 2364782
[patent_doc_number] => 04694321
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-09-15
[patent_title] => 'Semiconductor device having bipolar transistor and integrated injection logic'
[patent_app_type] => 1
[patent_app_number] => 6/755912
[patent_app_country] => US
[patent_app_date] => 1985-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2157
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/694/04694321.pdf
[firstpage_image] =>[orig_patent_app_number] => 755912
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/755912 | Semiconductor device having bipolar transistor and integrated injection logic | Jul 16, 1985 | Issued |
| 06/751557 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF PRODUCING THE SAME | Jul 2, 1985 | Abandoned |
| 06/746899 | SOLID PHASE EPITAXIAL GROWTH OF SINGLE CRYSTAL LAYERS ON SEMICONDUCTOR SUBSTRATES, USE AS AN OHMIC CONTACT AND METHOD OF PRODUCING SAME | Jun 19, 1985 | Abandoned |
Array
(
[id] => 2224136
[patent_doc_number] => 04595941
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-06-17
[patent_title] => 'Protection circuit for integrated circuit devices'
[patent_app_type] => 1
[patent_app_number] => 6/741703
[patent_app_country] => US
[patent_app_date] => 1985-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 1415
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 308
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/595/04595941.pdf
[firstpage_image] =>[orig_patent_app_number] => 741703
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/741703 | Protection circuit for integrated circuit devices | Jun 6, 1985 | Issued |
Array
(
[id] => 2420787
[patent_doc_number] => 04743954
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-05-10
[patent_title] => 'Integrated circuit for a chemical-selective sensor with voltage output'
[patent_app_type] => 1
[patent_app_number] => 6/742721
[patent_app_country] => US
[patent_app_date] => 1985-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 25
[patent_no_of_words] => 11939
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/743/04743954.pdf
[firstpage_image] =>[orig_patent_app_number] => 742721
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/742721 | Integrated circuit for a chemical-selective sensor with voltage output | Jun 6, 1985 | Issued |
| 06/737628 | SEMICONDUCTOR DEVICE FOR DETECTING ELECTROMAGNETIC RADIATION OR PARTICLES | May 21, 1985 | Abandoned |
Array
(
[id] => 2426361
[patent_doc_number] => 04734751
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-03-29
[patent_title] => 'Signal scaling MESFET of a segmented dual gate design'
[patent_app_type] => 1
[patent_app_number] => 6/735991
[patent_app_country] => US
[patent_app_date] => 1985-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 7325
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 442
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/734/04734751.pdf
[firstpage_image] =>[orig_patent_app_number] => 735991
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/735991 | Signal scaling MESFET of a segmented dual gate design | May 19, 1985 | Issued |
Array
(
[id] => 2152016
[patent_doc_number] => 04539490
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-09-03
[patent_title] => 'Charge pump substrate bias with antiparasitic guard ring'
[patent_app_type] => 1
[patent_app_number] => 6/494266
[patent_app_country] => US
[patent_app_date] => 1985-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 2865
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/539/04539490.pdf
[firstpage_image] =>[orig_patent_app_number] => 494266
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/494266 | Charge pump substrate bias with antiparasitic guard ring | May 12, 1985 | Issued |
Array
(
[id] => 2334574
[patent_doc_number] => 04635090
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-01-06
[patent_title] => 'Tapered groove IC isolation'
[patent_app_type] => 1
[patent_app_number] => 6/733406
[patent_app_country] => US
[patent_app_date] => 1985-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 16
[patent_no_of_words] => 4542
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/635/04635090.pdf
[firstpage_image] =>[orig_patent_app_number] => 733406
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/733406 | Tapered groove IC isolation | May 12, 1985 | Issued |