
William M. Brewster
Examiner (ID: 263)
| Most Active Art Unit | 2823 |
| Art Unit(s) | 2823, CSDE, 3716 |
| Total Applications | 771 |
| Issued Applications | 677 |
| Pending Applications | 8 |
| Abandoned Applications | 86 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5575508
[patent_doc_number] => 20090142870
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-06-04
[patent_title] => 'MANUFACTURING METHOD OF GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/302123
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/302123 | Manufacturing method of group III nitride semiconductor light-emitting device | Apr 30, 2008 | Issued |
Array
(
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[patent_doc_number] => 20080258165
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[patent_kind] => A1
[patent_issue_date] => 2008-10-23
[patent_title] => 'Light emitting diode chip'
[patent_app_type] => utility
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[patent_app_date] => 2008-04-22
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Array
(
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[patent_title] => 'Method for fabricating a light emitting diode chip'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/148894 | Method for fabricating a light emitting diode chip including etching by a laser beam | Apr 21, 2008 | Issued |
Array
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[patent_issue_date] => 2009-10-15
[patent_title] => 'METHOD OF SELECTIVELY ADJUSTING ION IMPLANTATION DOSE ON SEMICONDUCTOR DEVICES'
[patent_app_type] => utility
[patent_app_number] => 12/101323
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/101323 | Method of selectively adjusting ion implantation dose on semiconductor devices | Apr 10, 2008 | Issued |
Array
(
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[patent_title] => 'Method of manufacturing thin film transistor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/078693 | Method of manufacturing thin film transistor including forming a bank for ink jet printing | Apr 3, 2008 | Issued |
Array
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[patent_title] => 'Method of Forming Electrical Interconnects within Insulating Layers that Form Consecutive Sidewalls'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/051223 | Method of forming electrical interconnects within insulating layers that form consecutive sidewalls including forming a reaction layer on the inner sidewall | Mar 18, 2008 | Issued |
Array
(
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[patent_doc_number] => 20090233441
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[patent_issue_date] => 2009-09-17
[patent_title] => 'INTERCONNECTIONS FOR INTEGRATED CIRCUITS'
[patent_app_type] => utility
[patent_app_number] => 12/048223
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/048223 | Interconnections for integrated circuits including reducing an overburden and annealing | Mar 13, 2008 | Issued |
Array
(
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[patent_issue_date] => 2008-09-25
[patent_title] => 'Semiconductor integrated circuit production method and device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/073493 | Semiconductor integrated circuit production method and device including preparing a plurality of SOI substrates, grouping SOI substrates having mutual similarities and adjusting their layer thicknesses simultaneously | Mar 5, 2008 | Issued |
Array
(
[id] => 13426
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/073393 | Method of manufacturing nitride semiconductor light-emitting device | Mar 4, 2008 | Issued |
Array
(
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[patent_issue_date] => 2011-07-19
[patent_title] => 'Method of fabricating a memory cell'
[patent_app_type] => utility
[patent_app_number] => 12/039744
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/039744 | Method of fabricating a memory cell | Feb 28, 2008 | Issued |
Array
(
[id] => 5527317
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[patent_title] => 'WAFER PROCESSING'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/025623 | Wafer processing including dicing | Feb 3, 2008 | Issued |
Array
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Array
(
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Array
(
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[patent_issue_date] => 2009-06-18
[patent_title] => 'PARTICLE DISPLAY WITH JET-PRINTED COLOR FILTERS AND SURFACE COATINGS'
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Array
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Array
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Array
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Array
(
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