
William M. Brewster
Examiner (ID: 14871)
| Most Active Art Unit | 2823 |
| Art Unit(s) | 3716, CSDE, 2823 |
| Total Applications | 771 |
| Issued Applications | 677 |
| Pending Applications | 8 |
| Abandoned Applications | 86 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4719553
[patent_doc_number] => 20080242076
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-02
[patent_title] => 'METHOD OF MAKING SEMICONDUCTOR DIE STACK HAVING HEIGHTENED CONTACT FOR WIRE BOND'
[patent_app_type] => utility
[patent_app_number] => 11/693654
[patent_app_country] => US
[patent_app_date] => 2007-03-29
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0242/20080242076.pdf
[firstpage_image] =>[orig_patent_app_number] => 11693654
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/693654 | METHOD OF MAKING SEMICONDUCTOR DIE STACK HAVING HEIGHTENED CONTACT FOR WIRE BOND | Mar 28, 2007 | Abandoned |
Array
(
[id] => 162333
[patent_doc_number] => 07670930
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-02
[patent_title] => 'Method of detaching a thin film by melting precipitates'
[patent_app_type] => utility
[patent_app_number] => 12/293193
[patent_app_country] => US
[patent_app_date] => 2007-03-28
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[pdf_file] => patents/07/670/07670930.pdf
[firstpage_image] =>[orig_patent_app_number] => 12293193
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/293193 | Method of detaching a thin film by melting precipitates | Mar 27, 2007 | Issued |
Array
(
[id] => 4740057
[patent_doc_number] => 20080233710
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-25
[patent_title] => 'METHODS FOR FORMING SINGLE DIES WITH MULTI-LAYER INTERCONNECT STRUCTURES AND STRUCTURES FORMED THEREFROM'
[patent_app_type] => utility
[patent_app_number] => 11/689264
[patent_app_country] => US
[patent_app_date] => 2007-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[pdf_file] => publications/A1/0233/20080233710.pdf
[firstpage_image] =>[orig_patent_app_number] => 11689264
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/689264 | Methods for forming single dies with multi-layer interconnect structures and structures formed therefrom | Mar 20, 2007 | Issued |
Array
(
[id] => 5101344
[patent_doc_number] => 20070184606
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-08-09
[patent_title] => 'METHOD OF FORMING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/671994
[patent_app_country] => US
[patent_app_date] => 2007-02-06
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[firstpage_image] =>[orig_patent_app_number] => 11671994
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/671994 | Method of forming semiconductor device includeing forming control gate layer over each region and removing a portion of the tunnel insulating layer on the low voltage region | Feb 5, 2007 | Issued |
Array
(
[id] => 4845970
[patent_doc_number] => 20080182378
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[patent_kind] => A1
[patent_issue_date] => 2008-07-31
[patent_title] => 'METHOD OF PRODUCING AN INTEGRATED CIRCUIT HAVING A CAPACITOR'
[patent_app_type] => utility
[patent_app_number] => 11/669613
[patent_app_country] => US
[patent_app_date] => 2007-01-31
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[pdf_file] => publications/A1/0182/20080182378.pdf
[firstpage_image] =>[orig_patent_app_number] => 11669613
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/669613 | Method of producing an integrated circuit having a capacitor with a supporting layer | Jan 30, 2007 | Issued |
Array
(
[id] => 256272
[patent_doc_number] => 07575945
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-08-18
[patent_title] => 'Method of forming a metal line and method of manufacturing a display substrate by using the same including etching and undercutting the channel layer'
[patent_app_type] => utility
[patent_app_number] => 11/669653
[patent_app_country] => US
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[pdf_file] => patents/07/575/07575945.pdf
[firstpage_image] =>[orig_patent_app_number] => 11669653
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/669653 | Method of forming a metal line and method of manufacturing a display substrate by using the same including etching and undercutting the channel layer | Jan 30, 2007 | Issued |
Array
(
[id] => 5293705
[patent_doc_number] => 20090008631
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-01-08
[patent_title] => 'NANOWIRE TUNNELING TRANSISTOR'
[patent_app_type] => utility
[patent_app_number] => 12/161574
[patent_app_country] => US
[patent_app_date] => 2007-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[pdf_file] => publications/A1/0008/20090008631.pdf
[firstpage_image] =>[orig_patent_app_number] => 12161574
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/161574 | Nanowire tunneling transistor | Jan 23, 2007 | Issued |
Array
(
[id] => 33613
[patent_doc_number] => 07791129
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[patent_kind] => B2
[patent_issue_date] => 2010-09-07
[patent_title] => 'Semiconductor device and method of producing the same including a charge accumulation layer with differing charge trap surface density'
[patent_app_type] => utility
[patent_app_number] => 12/162224
[patent_app_country] => US
[patent_app_date] => 2007-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
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[pdf_file] => patents/07/791/07791129.pdf
[firstpage_image] =>[orig_patent_app_number] => 12162224
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/162224 | Semiconductor device and method of producing the same including a charge accumulation layer with differing charge trap surface density | Jan 17, 2007 | Issued |
Array
(
[id] => 5116068
[patent_doc_number] => 20070137781
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-21
[patent_title] => 'PACKAGE METHOD OF ORGANIC ELECTROLUMINESCENT DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/621484
[patent_app_country] => US
[patent_app_date] => 2007-01-09
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[pdf_file] => publications/A1/0137/20070137781.pdf
[firstpage_image] =>[orig_patent_app_number] => 11621484
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/621484 | PACKAGE METHOD OF ORGANIC ELECTROLUMINESCENT DEVICE | Jan 8, 2007 | Abandoned |
Array
(
[id] => 7530298
[patent_doc_number] => 07842520
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-30
[patent_title] => 'Method for manufacturing semiconductor device, semiconductor inspection device, and program including color imaging of metal silicide and calculations thereof'
[patent_app_type] => utility
[patent_app_number] => 11/615724
[patent_app_country] => US
[patent_app_date] => 2006-12-22
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[pdf_file] => patents/07/842/07842520.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/615724 | Method for manufacturing semiconductor device, semiconductor inspection device, and program including color imaging of metal silicide and calculations thereof | Dec 21, 2006 | Issued |
Array
(
[id] => 5040715
[patent_doc_number] => 20070092997
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-04-26
[patent_title] => 'FABRICATION METHOD OF NON-VOLATILE MEMORY'
[patent_app_type] => utility
[patent_app_number] => 11/614086
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/614086 | Fabrication method of non-volatile memory | Dec 20, 2006 | Issued |
Array
(
[id] => 5116829
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[patent_issue_date] => 2007-06-21
[patent_title] => 'SEMICONDUCTOR DEVICE'
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[patent_app_number] => 11/612723
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[firstpage_image] =>[orig_patent_app_number] => 11612723
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/612723 | Semiconductor device | Dec 18, 2006 | Issued |
Array
(
[id] => 4829241
[patent_doc_number] => 20080128777
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[patent_issue_date] => 2008-06-05
[patent_title] => 'TWO-STEP SELF-ALIGNED SOURCE ETCH WTIH LARGE PROCESS WINDOW'
[patent_app_type] => utility
[patent_app_number] => 11/611363
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[firstpage_image] =>[orig_patent_app_number] => 11611363
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/611363 | Two-step self-aligned source etch with large process window | Dec 14, 2006 | Issued |
Array
(
[id] => 4825901
[patent_doc_number] => 20080124856
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[patent_kind] => A1
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[patent_title] => 'Method of manufacturing semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/639344 | Method of manufacturing semiconductor device including forming two stress films and irradiation of one stress film | Dec 14, 2006 | Issued |
Array
(
[id] => 4883854
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[patent_title] => 'Source and Drain Formation in Silicon on Insulator Device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/158104 | Source and Drain Formation in Silicon on Insulator Device | Dec 11, 2006 | Abandoned |
Array
(
[id] => 5019491
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[patent_title] => 'System and Method of Forming A Split-Gate Flash Memory Structure'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/562731 | System and method of forming a split-gate flash memory structure including partial circular sidewalls of the floating gates and control gates | Nov 21, 2006 | Issued |
Array
(
[id] => 4820830
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/586234 | Production method for device | Oct 24, 2006 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/538173 | Flexible substrate with electronic devices and traces | Oct 2, 2006 | Issued |