Search

William M. Brewster

Examiner (ID: 14871)

Most Active Art Unit
2823
Art Unit(s)
3716, CSDE, 2823
Total Applications
771
Issued Applications
677
Pending Applications
8
Abandoned Applications
86

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4719553 [patent_doc_number] => 20080242076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'METHOD OF MAKING SEMICONDUCTOR DIE STACK HAVING HEIGHTENED CONTACT FOR WIRE BOND' [patent_app_type] => utility [patent_app_number] => 11/693654 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20080242076.pdf [firstpage_image] =>[orig_patent_app_number] => 11693654 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/693654
METHOD OF MAKING SEMICONDUCTOR DIE STACK HAVING HEIGHTENED CONTACT FOR WIRE BOND Mar 28, 2007 Abandoned
Array ( [id] => 162333 [patent_doc_number] => 07670930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-02 [patent_title] => 'Method of detaching a thin film by melting precipitates' [patent_app_type] => utility [patent_app_number] => 12/293193 [patent_app_country] => US [patent_app_date] => 2007-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 6059 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/670/07670930.pdf [firstpage_image] =>[orig_patent_app_number] => 12293193 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/293193
Method of detaching a thin film by melting precipitates Mar 27, 2007 Issued
Array ( [id] => 4740057 [patent_doc_number] => 20080233710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'METHODS FOR FORMING SINGLE DIES WITH MULTI-LAYER INTERCONNECT STRUCTURES AND STRUCTURES FORMED THEREFROM' [patent_app_type] => utility [patent_app_number] => 11/689264 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4734 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20080233710.pdf [firstpage_image] =>[orig_patent_app_number] => 11689264 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/689264
Methods for forming single dies with multi-layer interconnect structures and structures formed therefrom Mar 20, 2007 Issued
Array ( [id] => 5101344 [patent_doc_number] => 20070184606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'METHOD OF FORMING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/671994 [patent_app_country] => US [patent_app_date] => 2007-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7097 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20070184606.pdf [firstpage_image] =>[orig_patent_app_number] => 11671994 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/671994
Method of forming semiconductor device includeing forming control gate layer over each region and removing a portion of the tunnel insulating layer on the low voltage region Feb 5, 2007 Issued
Array ( [id] => 4845970 [patent_doc_number] => 20080182378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'METHOD OF PRODUCING AN INTEGRATED CIRCUIT HAVING A CAPACITOR' [patent_app_type] => utility [patent_app_number] => 11/669613 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4114 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20080182378.pdf [firstpage_image] =>[orig_patent_app_number] => 11669613 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/669613
Method of producing an integrated circuit having a capacitor with a supporting layer Jan 30, 2007 Issued
Array ( [id] => 256272 [patent_doc_number] => 07575945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-18 [patent_title] => 'Method of forming a metal line and method of manufacturing a display substrate by using the same including etching and undercutting the channel layer' [patent_app_type] => utility [patent_app_number] => 11/669653 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5663 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/575/07575945.pdf [firstpage_image] =>[orig_patent_app_number] => 11669653 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/669653
Method of forming a metal line and method of manufacturing a display substrate by using the same including etching and undercutting the channel layer Jan 30, 2007 Issued
Array ( [id] => 5293705 [patent_doc_number] => 20090008631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'NANOWIRE TUNNELING TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 12/161574 [patent_app_country] => US [patent_app_date] => 2007-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3690 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20090008631.pdf [firstpage_image] =>[orig_patent_app_number] => 12161574 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/161574
Nanowire tunneling transistor Jan 23, 2007 Issued
Array ( [id] => 33613 [patent_doc_number] => 07791129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Semiconductor device and method of producing the same including a charge accumulation layer with differing charge trap surface density' [patent_app_type] => utility [patent_app_number] => 12/162224 [patent_app_country] => US [patent_app_date] => 2007-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 32 [patent_no_of_words] => 9556 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/791/07791129.pdf [firstpage_image] =>[orig_patent_app_number] => 12162224 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/162224
Semiconductor device and method of producing the same including a charge accumulation layer with differing charge trap surface density Jan 17, 2007 Issued
Array ( [id] => 5116068 [patent_doc_number] => 20070137781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'PACKAGE METHOD OF ORGANIC ELECTROLUMINESCENT DEVICE' [patent_app_type] => utility [patent_app_number] => 11/621484 [patent_app_country] => US [patent_app_date] => 2007-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4075 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20070137781.pdf [firstpage_image] =>[orig_patent_app_number] => 11621484 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/621484
PACKAGE METHOD OF ORGANIC ELECTROLUMINESCENT DEVICE Jan 8, 2007 Abandoned
Array ( [id] => 7530298 [patent_doc_number] => 07842520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-30 [patent_title] => 'Method for manufacturing semiconductor device, semiconductor inspection device, and program including color imaging of metal silicide and calculations thereof' [patent_app_type] => utility [patent_app_number] => 11/615724 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 31 [patent_no_of_words] => 12770 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/842/07842520.pdf [firstpage_image] =>[orig_patent_app_number] => 11615724 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615724
Method for manufacturing semiconductor device, semiconductor inspection device, and program including color imaging of metal silicide and calculations thereof Dec 21, 2006 Issued
Array ( [id] => 5040715 [patent_doc_number] => 20070092997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'FABRICATION METHOD OF NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 11/614086 [patent_app_country] => US [patent_app_date] => 2006-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6787 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20070092997.pdf [firstpage_image] =>[orig_patent_app_number] => 11614086 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/614086
Fabrication method of non-volatile memory Dec 20, 2006 Issued
Array ( [id] => 5116829 [patent_doc_number] => 20070138543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/612723 [patent_app_country] => US [patent_app_date] => 2006-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10244 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20070138543.pdf [firstpage_image] =>[orig_patent_app_number] => 11612723 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/612723
Semiconductor device Dec 18, 2006 Issued
Array ( [id] => 4829241 [patent_doc_number] => 20080128777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'TWO-STEP SELF-ALIGNED SOURCE ETCH WTIH LARGE PROCESS WINDOW' [patent_app_type] => utility [patent_app_number] => 11/611363 [patent_app_country] => US [patent_app_date] => 2006-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5523 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20080128777.pdf [firstpage_image] =>[orig_patent_app_number] => 11611363 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/611363
Two-step self-aligned source etch with large process window Dec 14, 2006 Issued
Array ( [id] => 4825901 [patent_doc_number] => 20080124856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/639344 [patent_app_country] => US [patent_app_date] => 2006-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5569 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20080124856.pdf [firstpage_image] =>[orig_patent_app_number] => 11639344 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/639344
Method of manufacturing semiconductor device including forming two stress films and irradiation of one stress film Dec 14, 2006 Issued
Array ( [id] => 4883854 [patent_doc_number] => 20080258186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'Source and Drain Formation in Silicon on Insulator Device' [patent_app_type] => utility [patent_app_number] => 12/158104 [patent_app_country] => US [patent_app_date] => 2006-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1935 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20080258186.pdf [firstpage_image] =>[orig_patent_app_number] => 12158104 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/158104
Source and Drain Formation in Silicon on Insulator Device Dec 11, 2006 Abandoned
Array ( [id] => 5019491 [patent_doc_number] => 20070145457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'System and Method of Forming A Split-Gate Flash Memory Structure' [patent_app_type] => utility [patent_app_number] => 11/562731 [patent_app_country] => US [patent_app_date] => 2006-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3001 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20070145457.pdf [firstpage_image] =>[orig_patent_app_number] => 11562731 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/562731
System and method of forming a split-gate flash memory structure including partial circular sidewalls of the floating gates and control gates Nov 21, 2006 Issued
Array ( [id] => 4820830 [patent_doc_number] => 20080122091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'Semiconductor device and method for producing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/602024 [patent_app_country] => US [patent_app_date] => 2006-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7629 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20080122091.pdf [firstpage_image] =>[orig_patent_app_number] => 11602024 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/602024
Semiconductor device including a power device with first metal layer and second metal layer laterally spaced apart Nov 19, 2006 Issued
Array ( [id] => 131535 [patent_doc_number] => 07700444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-20 [patent_title] => 'Post-lithography misalignment correction with shadow effect for multiple patterning' [patent_app_type] => utility [patent_app_number] => 11/586274 [patent_app_country] => US [patent_app_date] => 2006-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2692 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/700/07700444.pdf [firstpage_image] =>[orig_patent_app_number] => 11586274 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/586274
Post-lithography misalignment correction with shadow effect for multiple patterning Oct 25, 2006 Issued
Array ( [id] => 184982 [patent_doc_number] => 07648889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-19 [patent_title] => 'Production method for device' [patent_app_type] => utility [patent_app_number] => 11/586234 [patent_app_country] => US [patent_app_date] => 2006-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 30 [patent_no_of_words] => 5874 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/648/07648889.pdf [firstpage_image] =>[orig_patent_app_number] => 11586234 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/586234
Production method for device Oct 24, 2006 Issued
Array ( [id] => 4745736 [patent_doc_number] => 20080090338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'FLEXIBLE SUBSTRATE WITH ELECTRONIC DEVICES AND TRACES' [patent_app_type] => utility [patent_app_number] => 11/538173 [patent_app_country] => US [patent_app_date] => 2006-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8404 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20080090338.pdf [firstpage_image] =>[orig_patent_app_number] => 11538173 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/538173
Flexible substrate with electronic devices and traces Oct 2, 2006 Issued
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