William M. Brewster

Array ( [id] => 6912430 [patent_doc_number] => 20050176188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-11 [patent_title] => 'Thin film transistor and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 10/777564 [patent_app_country] => US [patent_app_date] => 2004-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3734 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20050176188.pdf [firstpage_image] =>[orig_patent_app_number] => 10777564 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1012647 [patent_doc_number] => 06897118 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-24 [patent_title] => 'Method of multiple pulse laser annealing to activate ultra-shallow junctions' [patent_app_type] => utility [patent_app_number] => 10/776794 [patent_app_country] => US [patent_app_date] => 2004-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4389 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/897/06897118.pdf [firstpage_image] =>[orig_patent_app_number] => 10776794 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7235347 [patent_doc_number] => 20040157413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Semiconductor film, semiconductor device, and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/771404 [patent_app_country] => US [patent_app_date] => 2004-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13023 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20040157413.pdf [firstpage_image] =>[orig_patent_app_number] => 10771404 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7607619 [patent_doc_number] => 07098095 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-29 [patent_title] => 'Method of forming a MOS transistor with a layer of silicon germanium carbon' [patent_app_type] => utility [patent_app_number] => 10/772863 [patent_app_country] => US [patent_app_date] => 2004-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2306 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/098/07098095.pdf [firstpage_image] =>[orig_patent_app_number] => 10772863 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 485410 [patent_doc_number] => 07217594 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-15 [patent_title] => 'Alternative flip chip in leaded molded package design and method for manufacture' [patent_app_type] => utility [patent_app_number] => 10/772064 [patent_app_country] => US [patent_app_date] => 2004-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 3383 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/217/07217594.pdf [firstpage_image] =>[orig_patent_app_number] => 10772064 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 754208 [patent_doc_number] => 07018856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-28 [patent_title] => 'Calibration standards for dopants/impurities in silicon and preparation method' [patent_app_type] => utility [patent_app_number] => 10/768882 [patent_app_country] => US [patent_app_date] => 2004-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3548 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/018/07018856.pdf [firstpage_image] =>[orig_patent_app_number] => 10768882 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 715492 [patent_doc_number] => 07052963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-30 [patent_title] => 'Method of forming trench transistor with chained implanted body including a plurality of implantation with different energies' [patent_app_type] => utility [patent_app_number] => 10/767030 [patent_app_country] => US [patent_app_date] => 2004-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 90 [patent_no_of_words] => 16788 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/052/07052963.pdf [firstpage_image] =>[orig_patent_app_number] => 10767030 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 496697 [patent_doc_number] => 07208347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-24 [patent_title] => 'Connection technology for power semiconductors comprising a layer of electrically insulating material that follows the surface contours' [patent_app_type] => utility [patent_app_number] => 10/547173 [patent_app_country] => US [patent_app_date] => 2004-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4065 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/208/07208347.pdf [firstpage_image] =>[orig_patent_app_number] => 10547173 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 620068 [patent_doc_number] => 07141483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-28 [patent_title] => 'Nitrous oxide anneal of TEOS/ozone CVD for improved gapfill' [patent_app_type] => utility [patent_app_number] => 10/757771 [patent_app_country] => US [patent_app_date] => 2004-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5980 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/141/07141483.pdf [firstpage_image] =>[orig_patent_app_number] => 10757771 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1037472 [patent_doc_number] => 06872621 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-29 [patent_title] => 'Method for removal of hemispherical grained silicon in a deep trench' [patent_app_type] => utility [patent_app_number] => 10/758624 [patent_app_country] => US [patent_app_date] => 2004-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1588 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/872/06872621.pdf [firstpage_image] =>[orig_patent_app_number] => 10758624 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 650949 [patent_doc_number] => 07112526 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-26 [patent_title] => 'Manufacturing of a semiconductor device with a reduced capacitance between wirings' [patent_app_type] => utility [patent_app_number] => 10/757172 [patent_app_country] => US [patent_app_date] => 2004-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 4693 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/112/07112526.pdf [firstpage_image] =>[orig_patent_app_number] => 10757172 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 728235 [patent_doc_number] => 07041515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-09 [patent_title] => 'Balancing planarization of layers and the effect of underlying structure on the metrology signal' [patent_app_type] => utility [patent_app_number] => 10/757689 [patent_app_country] => US [patent_app_date] => 2004-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 5506 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/041/07041515.pdf [firstpage_image] =>[orig_patent_app_number] => 10757689 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7428812 [patent_doc_number] => 20040209389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-21 [patent_title] => 'Manufacturing method for liquid crystal display panels having high aperture ratio' [patent_app_type] => new [patent_app_number] => 10/752502 [patent_app_country] => US [patent_app_date] => 2004-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2327 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20040209389.pdf [firstpage_image] =>[orig_patent_app_number] => 10752502 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7304859 [patent_doc_number] => 20040140494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-22 [patent_title] => 'Contact structure' [patent_app_type] => new [patent_app_number] => 10/753041 [patent_app_country] => US [patent_app_date] => 2004-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3460 [patent_no_of_claims] => 87 [patent_no_of_ind_claims] => 29 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20040140494.pdf [firstpage_image] =>[orig_patent_app_number] => 10753041 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7074889 [patent_doc_number] => 20050148157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Backside unlayering of MOSFET devices for electrical and physical characterization' [patent_app_type] => utility [patent_app_number] => 10/752162 [patent_app_country] => US [patent_app_date] => 2004-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6618 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20050148157.pdf [firstpage_image] =>[orig_patent_app_number] => 10752162 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7074938 [patent_doc_number] => 20050148206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Atomic layer deposition using photo-enhanced bond reconfiguration' [patent_app_type] => utility [patent_app_number] => 10/749347 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 3798 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20050148206.pdf [firstpage_image] =>[orig_patent_app_number] => 10749347 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7253138 [patent_doc_number] => 20050142695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Induction-based heating for chip attach' [patent_app_type] => utility [patent_app_number] => 10/748344 [patent_app_country] => US [patent_app_date] => 2003-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2599 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20050142695.pdf [firstpage_image] =>[orig_patent_app_number] => 10748344 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7253134 [patent_doc_number] => 20050142694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'STACKING MEMORY CHIPS USING FLAT LEAD-FRAME WITH BREAKAWAY INSERTION PINS AND PIN-TO-PIN BRIDGES' [patent_app_type] => utility [patent_app_number] => 10/707624 [patent_app_country] => US [patent_app_date] => 2003-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4868 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20050142694.pdf [firstpage_image] =>[orig_patent_app_number] => 10707624 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1040573 [patent_doc_number] => 06869871 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-22 [patent_title] => 'Method of forming metal line in semiconductor device including forming first and second zirconium films' [patent_app_type] => utility [patent_app_number] => 10/744494 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2920 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/869/06869871.pdf [firstpage_image] =>[orig_patent_app_number] => 10744494 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 724507 [patent_doc_number] => 07045456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'MOS transistor gates with thin lower metal silicide and methods for making the same' [patent_app_type] => utility [patent_app_number] => 10/745454 [patent_app_country] => US [patent_app_date] => 2003-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 37 [patent_no_of_words] => 9665 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/045/07045456.pdf [firstpage_image] =>[orig_patent_app_number] => 10745454 [rel_patent_id] =>[rel_patent_doc_number] =>)