Search

William M. Brewster

Examiner (ID: 5627)

Most Active Art Unit
2823
Art Unit(s)
CSDE, 3716, 2823
Total Applications
771
Issued Applications
677
Pending Applications
8
Abandoned Applications
86

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7130208 [patent_doc_number] => 20040041237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Lateral high-voltage semiconductor devices with surface covered by thin film of dielectric material with high permittivity' [patent_app_type] => new [patent_app_number] => 10/652414 [patent_app_country] => US [patent_app_date] => 2003-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9727 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 370 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20040041237.pdf [firstpage_image] =>[orig_patent_app_number] => 10652414 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/652414
Lateral high-voltage semiconductor devices with surface covered by thin film of dielectric material with high permittivity Aug 28, 2003 Issued
Array ( [id] => 715477 [patent_doc_number] => 07052954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-30 [patent_title] => 'Method of fabricating a MOS structure with two conductive layers on the gate electrode' [patent_app_type] => utility [patent_app_number] => 10/650703 [patent_app_country] => US [patent_app_date] => 2003-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 49 [patent_no_of_words] => 8050 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/052/07052954.pdf [firstpage_image] =>[orig_patent_app_number] => 10650703 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/650703
Method of fabricating a MOS structure with two conductive layers on the gate electrode Aug 28, 2003 Issued
Array ( [id] => 7203797 [patent_doc_number] => 20040087095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-06 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => new [patent_app_number] => 10/647284 [patent_app_country] => US [patent_app_date] => 2003-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4761 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20040087095.pdf [firstpage_image] =>[orig_patent_app_number] => 10647284 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/647284
Method for fabricating a semiconductor device including using a hard mask or a silylated photoresist for an angled tilted ion implant Aug 25, 2003 Issued
Array ( [id] => 719977 [patent_doc_number] => 07049223 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-23 [patent_title] => 'Paste including a mixture of powders, connection plug, burying method, and semiconductor device manufacturing method' [patent_app_type] => utility [patent_app_number] => 10/646703 [patent_app_country] => US [patent_app_date] => 2003-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 27 [patent_no_of_words] => 8657 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/049/07049223.pdf [firstpage_image] =>[orig_patent_app_number] => 10646703 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/646703
Paste including a mixture of powders, connection plug, burying method, and semiconductor device manufacturing method Aug 24, 2003 Issued
Array ( [id] => 694618 [patent_doc_number] => 07071012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-04 [patent_title] => 'Methods relating to the reconstruction of semiconductor wafers for wafer-level processing' [patent_app_type] => utility [patent_app_number] => 10/645389 [patent_app_country] => US [patent_app_date] => 2003-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 5389 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/071/07071012.pdf [firstpage_image] =>[orig_patent_app_number] => 10645389 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/645389
Methods relating to the reconstruction of semiconductor wafers for wafer-level processing Aug 20, 2003 Issued
Array ( [id] => 783351 [patent_doc_number] => 06992320 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-31 [patent_title] => 'Semiconductor optical device with quantum dots having internal tensile or compressive strain' [patent_app_type] => utility [patent_app_number] => 10/644803 [patent_app_country] => US [patent_app_date] => 2003-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3752 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/992/06992320.pdf [firstpage_image] =>[orig_patent_app_number] => 10644803 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/644803
Semiconductor optical device with quantum dots having internal tensile or compressive strain Aug 20, 2003 Issued
Array ( [id] => 1073667 [patent_doc_number] => 06838332 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-04 [patent_title] => 'Method for forming a semiconductor device having electrical contact from opposite sides' [patent_app_type] => utility [patent_app_number] => 10/641544 [patent_app_country] => US [patent_app_date] => 2003-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 4095 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/838/06838332.pdf [firstpage_image] =>[orig_patent_app_number] => 10641544 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/641544
Method for forming a semiconductor device having electrical contact from opposite sides Aug 14, 2003 Issued
Array ( [id] => 6969712 [patent_doc_number] => 20050035422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-17 [patent_title] => 'METHOD FOR FORMING LIGHT SHIELD PROCESS FOR SOLID-STATE IMAGE SENSOR WITH MULTI-METALLIZATION LAYER' [patent_app_type] => utility [patent_app_number] => 10/641724 [patent_app_country] => US [patent_app_date] => 2003-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1143 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20050035422.pdf [firstpage_image] =>[orig_patent_app_number] => 10641724 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/641724
Method for forming light shield process for solid-state image sensor with multi-metallization layer Aug 14, 2003 Issued
Array ( [id] => 7313556 [patent_doc_number] => 20040033640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-19 [patent_title] => 'Solid state image device and manufacturing method thereof' [patent_app_type] => new [patent_app_number] => 10/637664 [patent_app_country] => US [patent_app_date] => 2003-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8334 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20040033640.pdf [firstpage_image] =>[orig_patent_app_number] => 10637664 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/637664
Solid state image device and including an optical lens and a microlens Aug 10, 2003 Issued
Array ( [id] => 1005354 [patent_doc_number] => 06905949 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-14 [patent_title] => 'Semiconductor apparatus fabrication method forming a resist pattern, a film over the resist, and reflowing the resist' [patent_app_type] => utility [patent_app_number] => 10/634824 [patent_app_country] => US [patent_app_date] => 2003-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 25 [patent_no_of_words] => 5045 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/905/06905949.pdf [firstpage_image] =>[orig_patent_app_number] => 10634824 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/634824
Semiconductor apparatus fabrication method forming a resist pattern, a film over the resist, and reflowing the resist Aug 5, 2003 Issued
Array ( [id] => 7400494 [patent_doc_number] => 20040023448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Process for production of SOI substrate and process for production of semiconductor device' [patent_app_type] => new [patent_app_number] => 10/632930 [patent_app_country] => US [patent_app_date] => 2003-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4655 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20040023448.pdf [firstpage_image] =>[orig_patent_app_number] => 10632930 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/632930
Process for production of SOI substrate and process for production of semiconductor device Aug 3, 2003 Issued
Array ( [id] => 7395266 [patent_doc_number] => 20040038512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Method for implementing selected functionality on an integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/633923 [patent_app_country] => US [patent_app_date] => 2003-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3012 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20040038512.pdf [firstpage_image] =>[orig_patent_app_number] => 10633923 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/633923
Method for implementing selected functionality on an integrated circuit device Aug 3, 2003 Issued
Array ( [id] => 737320 [patent_doc_number] => 07033931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-25 [patent_title] => 'Temperature optimization of a physical vapor deposition process to prevent extrusion into openings' [patent_app_type] => utility [patent_app_number] => 10/633334 [patent_app_country] => US [patent_app_date] => 2003-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 4789 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/033/07033931.pdf [firstpage_image] =>[orig_patent_app_number] => 10633334 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/633334
Temperature optimization of a physical vapor deposition process to prevent extrusion into openings Jul 31, 2003 Issued
Array ( [id] => 7386842 [patent_doc_number] => 20040021228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Method for forming a memory integrated circuit' [patent_app_type] => new [patent_app_number] => 10/631515 [patent_app_country] => US [patent_app_date] => 2003-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4544 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20040021228.pdf [firstpage_image] =>[orig_patent_app_number] => 10631515 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/631515
Method for forming a memory integrated circuit with bitlines over gates and capacitors over bitlines Jul 30, 2003 Issued
Array ( [id] => 1123262 [patent_doc_number] => 06794219 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-21 [patent_title] => 'Method for creating a lateral overflow drain, anti-blooming structure in a charge coupled device' [patent_app_type] => B1 [patent_app_number] => 10/628184 [patent_app_country] => US [patent_app_date] => 2003-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2667 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/794/06794219.pdf [firstpage_image] =>[orig_patent_app_number] => 10628184 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/628184
Method for creating a lateral overflow drain, anti-blooming structure in a charge coupled device Jul 27, 2003 Issued
Array ( [id] => 7204140 [patent_doc_number] => 20040087150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-06 [patent_title] => 'Structural element and process for its production' [patent_app_type] => new [patent_app_number] => 10/621011 [patent_app_country] => US [patent_app_date] => 2003-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2683 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20040087150.pdf [firstpage_image] =>[orig_patent_app_number] => 10621011 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/621011
Structural element and process for its production including bonding through an amorphous hard layer Jul 15, 2003 Issued
Array ( [id] => 1095865 [patent_doc_number] => 06821818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-23 [patent_title] => 'Method of assembling a semiconductor device including sweeping (with a squeegee) encapsulant over the device repeatedly' [patent_app_type] => B2 [patent_app_number] => 10/619334 [patent_app_country] => US [patent_app_date] => 2003-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 29 [patent_no_of_words] => 5659 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/821/06821818.pdf [firstpage_image] =>[orig_patent_app_number] => 10619334 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/619334
Method of assembling a semiconductor device including sweeping (with a squeegee) encapsulant over the device repeatedly Jul 13, 2003 Issued
Array ( [id] => 7120344 [patent_doc_number] => 20050012173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-20 [patent_title] => 'Narrow width effect improvement with photoresist plug process and STI corner ion implantation' [patent_app_type] => utility [patent_app_number] => 10/619114 [patent_app_country] => US [patent_app_date] => 2003-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5640 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20050012173.pdf [firstpage_image] =>[orig_patent_app_number] => 10619114 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/619114
Narrow width effect improvement with photoresist plug process and STI corner ion implantation Jul 13, 2003 Issued
Array ( [id] => 7395199 [patent_doc_number] => 20040038501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Semiconductor device and active matrix type display' [patent_app_type] => new [patent_app_number] => 10/618163 [patent_app_country] => US [patent_app_date] => 2003-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6669 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20040038501.pdf [firstpage_image] =>[orig_patent_app_number] => 10618163 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/618163
Method of forming active matrix type display including a metal layer having a light shield function Jul 10, 2003 Issued
Array ( [id] => 7089114 [patent_doc_number] => 20050009227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Organic semiconductor devices and methods of fabrication' [patent_app_type] => utility [patent_app_number] => 10/617413 [patent_app_country] => US [patent_app_date] => 2003-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4855 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20050009227.pdf [firstpage_image] =>[orig_patent_app_number] => 10617413 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/617413
Organic semiconductor devices and methods of fabrication including forming two parts with polymerisable groups and bonding the parts Jul 10, 2003 Issued
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