
William M. Brewster
Examiner (ID: 3831)
| Most Active Art Unit | 2823 |
| Art Unit(s) | 3716, CSDE, 2823 |
| Total Applications | 771 |
| Issued Applications | 677 |
| Pending Applications | 8 |
| Abandoned Applications | 86 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6647074
[patent_doc_number] => 20030075776
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-04-24
[patent_title] => 'Integrated circuit and manufacturing method thereof'
[patent_app_type] => new
[patent_app_number] => 10/273313
[patent_app_country] => US
[patent_app_date] => 2002-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7817
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[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0075/20030075776.pdf
[firstpage_image] =>[orig_patent_app_number] => 10273313
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/273313 | Integrated circuit including an inductor, active layers with isolation dielectrics, and multiple insulation layers | Oct 16, 2002 | Issued |
Array
(
[id] => 7204107
[patent_doc_number] => 20040087144
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-06
[patent_title] => 'Cobalt silicide formation method employing wet chemical silicon substrate oxidation'
[patent_app_type] => new
[patent_app_number] => 10/269283
[patent_app_country] => US
[patent_app_date] => 2002-10-12
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0087/20040087144.pdf
[firstpage_image] =>[orig_patent_app_number] => 10269283
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/269283 | Cobalt silicide formation method employing wet chemical silicon substrate oxidation | Oct 11, 2002 | Issued |
Array
(
[id] => 1273671
[patent_doc_number] => 06649441
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-11-18
[patent_title] => 'Method for fabricating a microcontact spring on a substrate'
[patent_app_type] => B2
[patent_app_number] => 10/267224
[patent_app_country] => US
[patent_app_date] => 2002-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/649/06649441.pdf
[firstpage_image] =>[orig_patent_app_number] => 10267224
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/267224 | Method for fabricating a microcontact spring on a substrate | Oct 8, 2002 | Issued |
Array
(
[id] => 6832780
[patent_doc_number] => 20030160325
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-28
[patent_title] => 'Semiconductor device substrate and manufacturing method thereof and semiconductor package'
[patent_app_type] => new
[patent_app_number] => 10/262074
[patent_app_country] => US
[patent_app_date] => 2002-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
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[patent_no_of_words] => 6122
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[pdf_file] => publications/A1/0160/20030160325.pdf
[firstpage_image] =>[orig_patent_app_number] => 10262074
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/262074 | Semiconductor device and package including forming pyramid mount protruding through silicon substrate | Oct 1, 2002 | Issued |
Array
(
[id] => 1212799
[patent_doc_number] => 06709965
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-03-23
[patent_title] => 'Aluminum-copper bond pad design and method of fabrication'
[patent_app_type] => B1
[patent_app_number] => 10/262923
[patent_app_country] => US
[patent_app_date] => 2002-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/06/709/06709965.pdf
[firstpage_image] =>[orig_patent_app_number] => 10262923
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/262923 | Aluminum-copper bond pad design and method of fabrication | Oct 1, 2002 | Issued |
Array
(
[id] => 1269958
[patent_doc_number] => 06653156
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-11-25
[patent_title] => 'Ferroelectric device with capping layer and method of making same'
[patent_app_type] => B2
[patent_app_number] => 10/262034
[patent_app_country] => US
[patent_app_date] => 2002-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/06/653/06653156.pdf
[firstpage_image] =>[orig_patent_app_number] => 10262034
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/262034 | Ferroelectric device with capping layer and method of making same | Sep 29, 2002 | Issued |
Array
(
[id] => 1101662
[patent_doc_number] => 06815298
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-11-09
[patent_title] => 'Method of forming a semiconductor device including forming an amorphous silicon layer over and reacting with a silicide layer'
[patent_app_type] => B2
[patent_app_number] => 10/256164
[patent_app_country] => US
[patent_app_date] => 2002-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 7736
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[pdf_file] => patents/06/815/06815298.pdf
[firstpage_image] =>[orig_patent_app_number] => 10256164
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/256164 | Method of forming a semiconductor device including forming an amorphous silicon layer over and reacting with a silicide layer | Sep 26, 2002 | Issued |
Array
(
[id] => 7264006
[patent_doc_number] => 20040241900
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-02
[patent_title] => 'Organic semiconductor material and organic semiconductor element employing the same'
[patent_app_type] => new
[patent_app_number] => 10/491084
[patent_app_country] => US
[patent_app_date] => 2004-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 7093
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[pdf_file] => publications/A1/0241/20040241900.pdf
[firstpage_image] =>[orig_patent_app_number] => 10491084
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/491084 | Organic semiconductor material and organic semiconductor element employing the same including carbon nanotubes | Sep 24, 2002 | Issued |
Array
(
[id] => 6787796
[patent_doc_number] => 20030139035
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[patent_kind] => A1
[patent_issue_date] => 2003-07-24
[patent_title] => 'Low dielectric (low k) barrier films with oxygen doping by plasma-enhanced chemical vapor deposition (pecvd)'
[patent_app_type] => new
[patent_app_number] => 10/247404
[patent_app_country] => US
[patent_app_date] => 2002-09-19
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[pdf_file] => publications/A1/0139/20030139035.pdf
[firstpage_image] =>[orig_patent_app_number] => 10247404
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/247404 | Method for producing semiconductor including forming a layer containing at least silicon carbide and forming a second layer containing at least silicon oxygen carbide | Sep 18, 2002 | Issued |
Array
(
[id] => 6774334
[patent_doc_number] => 20030017672
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-23
[patent_title] => 'Nonvolatile memory device'
[patent_app_type] => new
[patent_app_number] => 10/245293
[patent_app_country] => US
[patent_app_date] => 2002-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
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[pdf_file] => publications/A1/0017/20030017672.pdf
[firstpage_image] =>[orig_patent_app_number] => 10245293
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/245293 | Nonvolatile memory device | Sep 17, 2002 | Abandoned |
Array
(
[id] => 1101615
[patent_doc_number] => 06815274
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-11-09
[patent_title] => 'Resist protect oxide structure of sub-micron salicide process'
[patent_app_type] => B1
[patent_app_number] => 10/243414
[patent_app_country] => US
[patent_app_date] => 2002-09-13
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[firstpage_image] =>[orig_patent_app_number] => 10243414
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/243414 | Resist protect oxide structure of sub-micron salicide process | Sep 12, 2002 | Issued |
Array
(
[id] => 1134435
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[patent_issue_date] => 2004-08-31
[patent_title] => 'Methods and apparatus for forming barrier layers in high aspect ratio vias'
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[patent_app_number] => 10/241373
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[firstpage_image] =>[orig_patent_app_number] => 10241373
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/241373 | Methods and apparatus for forming barrier layers in high aspect ratio vias | Sep 10, 2002 | Issued |
Array
(
[id] => 6811757
[patent_doc_number] => 20030071307
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[patent_issue_date] => 2003-04-17
[patent_title] => 'High performance poly-SiGe thin film transistor and a method of fabricating such a thin film transistor'
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[firstpage_image] =>[orig_patent_app_number] => 10232700
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/232700 | High performance poly-SiGe thin film transistor and a method of fabricating such a thin film transistor | Sep 2, 2002 | Issued |
Array
(
[id] => 779214
[patent_doc_number] => 06995081
[patent_country] => US
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[patent_issue_date] => 2006-02-07
[patent_title] => 'Systems and methods for forming tantalum silicide layers'
[patent_app_type] => utility
[patent_app_number] => 10/229813
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[firstpage_image] =>[orig_patent_app_number] => 10229813
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/229813 | Systems and methods for forming tantalum silicide layers | Aug 27, 2002 | Issued |
Array
(
[id] => 508902
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[patent_title] => 'Atomic layer deposited HfSiON dielectric films wherein each precursor is independendently pulsed'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/229903 | Atomic layer deposited HfSiON dielectric films wherein each precursor is independendently pulsed | Aug 27, 2002 | Issued |
Array
(
[id] => 6755911
[patent_doc_number] => 20030003688
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[patent_issue_date] => 2003-01-02
[patent_title] => 'Method and apparatus for marking a bare semiconductor die'
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[patent_app_number] => 10/227317
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/227317 | Method and apparatus for marking a bare semiconductor die | Aug 22, 2002 | Issued |
Array
(
[id] => 7400686
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[patent_issue_date] => 2004-02-05
[patent_title] => 'Electrolytic contact pads'
[patent_app_type] => new
[patent_app_number] => 10/211914
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/211914 | Method of forming electrolytic contact pads including layers of copper, nickel, and gold | Aug 4, 2002 | Issued |
Array
(
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[patent_title] => 'SEMICONDUCTOR DICE HAVING BACKSIDE REDISTRIBUTION LAYER ACCESSED USING THROUGH-SILICON VIAS, METHODS OF FABRICATION AND ASSEMBLIES'
[patent_app_type] => new
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[firstpage_image] =>[orig_patent_app_number] => 10209823
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/209823 | Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies | Jul 30, 2002 | Issued |
Array
(
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[patent_title] => 'Field effect transistor structure with self-aligned raised source/drain extensions'
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Array
(
[id] => 6829975
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[patent_title] => 'Masks and method for contact hole exposure'
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[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10199413
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/199413 | Masks and method for contact hole exposure | Jul 17, 2002 | Issued |