
William M. Brewster
Examiner (ID: 3831)
| Most Active Art Unit | 2823 |
| Art Unit(s) | 3716, CSDE, 2823 |
| Total Applications | 771 |
| Issued Applications | 677 |
| Pending Applications | 8 |
| Abandoned Applications | 86 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7028159
[patent_doc_number] => 20010014505
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-16
[patent_title] => 'Amorphous dielectric capacitors on silicon'
[patent_app_type] => new
[patent_app_number] => 09/841948
[patent_app_country] => US
[patent_app_date] => 2001-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 3036
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0014/20010014505.pdf
[firstpage_image] =>[orig_patent_app_number] => 09841948
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/841948 | Amorphous dielectric capacitors on silicon | Apr 24, 2001 | Abandoned |
Array
(
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[patent_doc_number] => 06642620
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-11-04
[patent_title] => 'Integrated circuits having low resistivity contacts and the formation thereof using an in situ plasma doping and clean'
[patent_app_type] => B1
[patent_app_number] => 09/839379
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/839379 | Integrated circuits having low resistivity contacts and the formation thereof using an in situ plasma doping and clean | Apr 19, 2001 | Issued |
Array
(
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[patent_doc_number] => 06455415
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[patent_kind] => B1
[patent_issue_date] => 2002-09-24
[patent_title] => 'Method of encapsulated copper (Cu) interconnect formation'
[patent_app_type] => B1
[patent_app_number] => 09/836054
[patent_app_country] => US
[patent_app_date] => 2001-04-16
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[firstpage_image] =>[orig_patent_app_number] => 09836054
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/836054 | Method of encapsulated copper (Cu) interconnect formation | Apr 15, 2001 | Issued |
Array
(
[id] => 6899615
[patent_doc_number] => 20010009291
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-07-26
[patent_title] => 'Semiconductor structure having reduced silicide resistance between closely spaced gates and method of fabrication'
[patent_app_type] => new
[patent_app_number] => 09/817143
[patent_app_country] => US
[patent_app_date] => 2001-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/817143 | Semiconductor structure having reduced silicide resistance between closely spaced gates and method of fabrication | Mar 26, 2001 | Abandoned |
Array
(
[id] => 7000507
[patent_doc_number] => 20010053568
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[patent_kind] => A1
[patent_issue_date] => 2001-12-20
[patent_title] => 'Method for manufacturing a semiconductor component'
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[patent_app_number] => 09/817594
[patent_app_country] => US
[patent_app_date] => 2001-03-26
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/817594 | Method for manufacturing a semiconductor component | Mar 25, 2001 | Issued |
Array
(
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[patent_issue_date] => 2002-01-10
[patent_title] => 'Submicron metallization using electrochemical deposition'
[patent_app_type] => new
[patent_app_number] => 09/815931
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 09815931
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/815931 | Submicron metallization using electrochemical deposition | Mar 22, 2001 | Issued |
Array
(
[id] => 6209288
[patent_doc_number] => 20020072193
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[patent_issue_date] => 2002-06-13
[patent_title] => 'Method of aligning a photolithographic mask to a crystal plane'
[patent_app_type] => new
[patent_app_number] => 09/799494
[patent_app_country] => US
[patent_app_date] => 2001-03-07
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/799494 | Method of aligning a photolithographic mask to a crystal plane | Mar 6, 2001 | Issued |
Array
(
[id] => 5968552
[patent_doc_number] => 20020090812
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-07-11
[patent_title] => 'Method for forming trench'
[patent_app_type] => new
[patent_app_number] => 09/799004
[patent_app_country] => US
[patent_app_date] => 2001-03-06
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 09799004
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/799004 | Method for forming trench including a first and a second layer of photoresist | Mar 5, 2001 | Issued |
Array
(
[id] => 6887797
[patent_doc_number] => 20010008791
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[patent_issue_date] => 2001-07-19
[patent_title] => 'High temperature pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on sapphire substrates'
[patent_app_type] => new-utility
[patent_app_number] => 09/780715
[patent_app_country] => US
[patent_app_date] => 2001-02-09
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[pdf_file] => publications/A1/0008/20010008791.pdf
[firstpage_image] =>[orig_patent_app_number] => 09780715
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/780715 | High temperature pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on sapphire substrates | Feb 8, 2001 | Issued |
Array
(
[id] => 6277185
[patent_doc_number] => 20020106880
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[patent_issue_date] => 2002-08-08
[patent_title] => 'Method for avoiding the junction leakage'
[patent_app_type] => new
[patent_app_number] => 09/776744
[patent_app_country] => US
[patent_app_date] => 2001-02-05
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[firstpage_image] =>[orig_patent_app_number] => 09776744
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/776744 | Method for avoiding the junction leakage | Feb 4, 2001 | Abandoned |
Array
(
[id] => 6898582
[patent_doc_number] => 20010046747
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[patent_issue_date] => 2001-11-29
[patent_title] => 'Heterojunction bipolar transistor and manufacturing method therefor'
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[patent_app_number] => 09/775593
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[firstpage_image] =>[orig_patent_app_number] => 09775593
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/775593 | Heterojunction bipolar transistor and manufacturing method therefor including electrode alloyed reaction layers | Feb 4, 2001 | Issued |
Array
(
[id] => 1409749
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[patent_title] => 'Thinning of trench and line or contact spacing by use of dual layer photoresist'
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Array
(
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[patent_title] => 'Method for improving alignment precision in forming color filter array'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/774463 | Method for improving alignment precision in forming color filter array | Jan 30, 2001 | Abandoned |
Array
(
[id] => 6016437
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[patent_title] => 'Method for manufacturing semiconductor device on silicon-on-insulator substrate'
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Array
(
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Array
(
[id] => 6894050
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[patent_title] => 'Method for fabricating contact plug'
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[patent_app_number] => 09/770304
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[firstpage_image] =>[orig_patent_app_number] => 09770304
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/770304 | Method for fabricating contact plug | Jan 28, 2001 | Abandoned |
Array
(
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Array
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Array
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Array
(
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