Search

William M. Brewster

Examiner (ID: 3831)

Most Active Art Unit
2823
Art Unit(s)
3716, CSDE, 2823
Total Applications
771
Issued Applications
677
Pending Applications
8
Abandoned Applications
86

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7028159 [patent_doc_number] => 20010014505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-16 [patent_title] => 'Amorphous dielectric capacitors on silicon' [patent_app_type] => new [patent_app_number] => 09/841948 [patent_app_country] => US [patent_app_date] => 2001-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3036 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20010014505.pdf [firstpage_image] =>[orig_patent_app_number] => 09841948 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/841948
Amorphous dielectric capacitors on silicon Apr 24, 2001 Abandoned
Array ( [id] => 1284721 [patent_doc_number] => 06642620 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Integrated circuits having low resistivity contacts and the formation thereof using an in situ plasma doping and clean' [patent_app_type] => B1 [patent_app_number] => 09/839379 [patent_app_country] => US [patent_app_date] => 2001-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3336 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/642/06642620.pdf [firstpage_image] =>[orig_patent_app_number] => 09839379 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/839379
Integrated circuits having low resistivity contacts and the formation thereof using an in situ plasma doping and clean Apr 19, 2001 Issued
Array ( [id] => 1450064 [patent_doc_number] => 06455415 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Method of encapsulated copper (Cu) interconnect formation' [patent_app_type] => B1 [patent_app_number] => 09/836054 [patent_app_country] => US [patent_app_date] => 2001-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3414 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/455/06455415.pdf [firstpage_image] =>[orig_patent_app_number] => 09836054 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/836054
Method of encapsulated copper (Cu) interconnect formation Apr 15, 2001 Issued
Array ( [id] => 6899615 [patent_doc_number] => 20010009291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-26 [patent_title] => 'Semiconductor structure having reduced silicide resistance between closely spaced gates and method of fabrication' [patent_app_type] => new [patent_app_number] => 09/817143 [patent_app_country] => US [patent_app_date] => 2001-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1903 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20010009291.pdf [firstpage_image] =>[orig_patent_app_number] => 09817143 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/817143
Semiconductor structure having reduced silicide resistance between closely spaced gates and method of fabrication Mar 26, 2001 Abandoned
Array ( [id] => 7000507 [patent_doc_number] => 20010053568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-20 [patent_title] => 'Method for manufacturing a semiconductor component' [patent_app_type] => new [patent_app_number] => 09/817594 [patent_app_country] => US [patent_app_date] => 2001-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10028 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20010053568.pdf [firstpage_image] =>[orig_patent_app_number] => 09817594 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/817594
Method for manufacturing a semiconductor component Mar 25, 2001 Issued
Array ( [id] => 6224726 [patent_doc_number] => 20020004301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'Submicron metallization using electrochemical deposition' [patent_app_type] => new [patent_app_number] => 09/815931 [patent_app_country] => US [patent_app_date] => 2001-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3229 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20020004301.pdf [firstpage_image] =>[orig_patent_app_number] => 09815931 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/815931
Submicron metallization using electrochemical deposition Mar 22, 2001 Issued
Array ( [id] => 6209288 [patent_doc_number] => 20020072193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Method of aligning a photolithographic mask to a crystal plane' [patent_app_type] => new [patent_app_number] => 09/799494 [patent_app_country] => US [patent_app_date] => 2001-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3093 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20020072193.pdf [firstpage_image] =>[orig_patent_app_number] => 09799494 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/799494
Method of aligning a photolithographic mask to a crystal plane Mar 6, 2001 Issued
Array ( [id] => 5968552 [patent_doc_number] => 20020090812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-11 [patent_title] => 'Method for forming trench' [patent_app_type] => new [patent_app_number] => 09/799004 [patent_app_country] => US [patent_app_date] => 2001-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1753 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20020090812.pdf [firstpage_image] =>[orig_patent_app_number] => 09799004 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/799004
Method for forming trench including a first and a second layer of photoresist Mar 5, 2001 Issued
Array ( [id] => 6887797 [patent_doc_number] => 20010008791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-19 [patent_title] => 'High temperature pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on sapphire substrates' [patent_app_type] => new-utility [patent_app_number] => 09/780715 [patent_app_country] => US [patent_app_date] => 2001-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5451 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20010008791.pdf [firstpage_image] =>[orig_patent_app_number] => 09780715 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/780715
High temperature pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on sapphire substrates Feb 8, 2001 Issued
Array ( [id] => 6277185 [patent_doc_number] => 20020106880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'Method for avoiding the junction leakage' [patent_app_type] => new [patent_app_number] => 09/776744 [patent_app_country] => US [patent_app_date] => 2001-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3086 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20020106880.pdf [firstpage_image] =>[orig_patent_app_number] => 09776744 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/776744
Method for avoiding the junction leakage Feb 4, 2001 Abandoned
Array ( [id] => 6898582 [patent_doc_number] => 20010046747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'Heterojunction bipolar transistor and manufacturing method therefor' [patent_app_type] => new [patent_app_number] => 09/775593 [patent_app_country] => US [patent_app_date] => 2001-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6886 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20010046747.pdf [firstpage_image] =>[orig_patent_app_number] => 09775593 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/775593
Heterojunction bipolar transistor and manufacturing method therefor including electrode alloyed reaction layers Feb 4, 2001 Issued
Array ( [id] => 1409749 [patent_doc_number] => 06528398 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Thinning of trench and line or contact spacing by use of dual layer photoresist' [patent_app_type] => B1 [patent_app_number] => 09/775084 [patent_app_country] => US [patent_app_date] => 2001-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3453 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/528/06528398.pdf [firstpage_image] =>[orig_patent_app_number] => 09775084 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/775084
Thinning of trench and line or contact spacing by use of dual layer photoresist Jan 31, 2001 Issued
Array ( [id] => 6016426 [patent_doc_number] => 20020102812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'Method for improving alignment precision in forming color filter array' [patent_app_type] => new [patent_app_number] => 09/774463 [patent_app_country] => US [patent_app_date] => 2001-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2319 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20020102812.pdf [firstpage_image] =>[orig_patent_app_number] => 09774463 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/774463
Method for improving alignment precision in forming color filter array Jan 30, 2001 Abandoned
Array ( [id] => 6016437 [patent_doc_number] => 20020102813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'Method for manufacturing semiconductor device on silicon-on-insulator substrate' [patent_app_type] => new [patent_app_number] => 09/774774 [patent_app_country] => US [patent_app_date] => 2001-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2097 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20020102813.pdf [firstpage_image] =>[orig_patent_app_number] => 09774774 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/774774
Method for manufacturing semiconductor device on silicon-on-insulator substrate Jan 30, 2001 Abandoned
Array ( [id] => 6016478 [patent_doc_number] => 20020102840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'Method for manufacturing cooper interconnects by using a cap layer' [patent_app_type] => new [patent_app_number] => 09/774464 [patent_app_country] => US [patent_app_date] => 2001-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1996 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20020102840.pdf [firstpage_image] =>[orig_patent_app_number] => 09774464 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/774464
Method for manufacturing cooper interconnects by using a cap layer Jan 30, 2001 Abandoned
Array ( [id] => 6894050 [patent_doc_number] => 20010016416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-23 [patent_title] => 'Method for fabricating contact plug' [patent_app_type] => new [patent_app_number] => 09/770304 [patent_app_country] => US [patent_app_date] => 2001-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2209 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20010016416.pdf [firstpage_image] =>[orig_patent_app_number] => 09770304 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/770304
Method for fabricating contact plug Jan 28, 2001 Abandoned
Array ( [id] => 6016448 [patent_doc_number] => 20020102814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'Trench fill process for reducing stress in shallow trench isolation' [patent_app_type] => new [patent_app_number] => 09/771084 [patent_app_country] => US [patent_app_date] => 2001-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4008 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20020102814.pdf [firstpage_image] =>[orig_patent_app_number] => 09771084 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/771084
Trench fill process for reducing stress in shallow trench isolation Jan 25, 2001 Issued
Array ( [id] => 1507325 [patent_doc_number] => 06440800 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layers' [patent_app_type] => B1 [patent_app_number] => 09/769814 [patent_app_country] => US [patent_app_date] => 2001-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 1971 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/440/06440800.pdf [firstpage_image] =>[orig_patent_app_number] => 09769814 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/769814
Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layers Jan 25, 2001 Issued
Array ( [id] => 6290449 [patent_doc_number] => 20020055236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Method for fabricating shallow trench isolation' [patent_app_type] => new [patent_app_number] => 09/768613 [patent_app_country] => US [patent_app_date] => 2001-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2016 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20020055236.pdf [firstpage_image] =>[orig_patent_app_number] => 09768613 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/768613
Method for fabricating shallow trench isolation Jan 24, 2001 Issued
Array ( [id] => 6895204 [patent_doc_number] => 20010025994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Process for producing semiconductor device and semiconductor device' [patent_app_type] => new [patent_app_number] => 09/766613 [patent_app_country] => US [patent_app_date] => 2001-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5052 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20010025994.pdf [firstpage_image] =>[orig_patent_app_number] => 09766613 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/766613
Process for producing semiconductor device and semiconductor device Jan 22, 2001 Abandoned
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