Search

William M. Brewster

Examiner (ID: 3831)

Most Active Art Unit
2823
Art Unit(s)
3716, CSDE, 2823
Total Applications
771
Issued Applications
677
Pending Applications
8
Abandoned Applications
86

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4214538 [patent_doc_number] => 06110790 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Method for making a MOSFET with self-aligned source and drain contacts including forming an oxide liner on the gate, forming nitride spacers on the liner, etching the liner, and forming contacts in the gaps' [patent_app_type] => 1 [patent_app_number] => 9/327093 [patent_app_country] => US [patent_app_date] => 1999-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1306 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/110/06110790.pdf [firstpage_image] =>[orig_patent_app_number] => 327093 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/327093
Method for making a MOSFET with self-aligned source and drain contacts including forming an oxide liner on the gate, forming nitride spacers on the liner, etching the liner, and forming contacts in the gaps Jun 3, 1999 Issued
Array ( [id] => 4302410 [patent_doc_number] => 06187624 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Method for making closely spaced capacitors with reduced parasitic capacitance on a dynamic random access memory (DRAM) device' [patent_app_type] => 1 [patent_app_number] => 9/325954 [patent_app_country] => US [patent_app_date] => 1999-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4547 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 369 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/187/06187624.pdf [firstpage_image] =>[orig_patent_app_number] => 325954 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/325954
Method for making closely spaced capacitors with reduced parasitic capacitance on a dynamic random access memory (DRAM) device Jun 3, 1999 Issued
Array ( [id] => 4253130 [patent_doc_number] => 06137139 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Low voltage dual-well MOS device having high ruggedness, low on-resistance, and improved body diode reverse recovery' [patent_app_type] => 1 [patent_app_number] => 9/324553 [patent_app_country] => US [patent_app_date] => 1999-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3016 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137139.pdf [firstpage_image] =>[orig_patent_app_number] => 324553 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/324553
Low voltage dual-well MOS device having high ruggedness, low on-resistance, and improved body diode reverse recovery Jun 2, 1999 Issued
Array ( [id] => 4290169 [patent_doc_number] => 06235624 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Paste connection plug, burying method, and semiconductor device manufacturing method' [patent_app_type] => 1 [patent_app_number] => 9/321534 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 27 [patent_no_of_words] => 8652 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/235/06235624.pdf [firstpage_image] =>[orig_patent_app_number] => 321534 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/321534
Paste connection plug, burying method, and semiconductor device manufacturing method May 27, 1999 Issued
09/322313 DISCRETE SCHOTTKY DIODE DEVICE WITH REDUCED LEAKAGE CURRENT May 27, 1999 Abandoned
Array ( [id] => 4345141 [patent_doc_number] => 06284675 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Method of forming integrated circuit dielectric by evaporating solvent to yield phase separation' [patent_app_type] => 1 [patent_app_number] => 9/320014 [patent_app_country] => US [patent_app_date] => 1999-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 2660 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/284/06284675.pdf [firstpage_image] =>[orig_patent_app_number] => 320014 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/320014
Method of forming integrated circuit dielectric by evaporating solvent to yield phase separation May 25, 1999 Issued
Array ( [id] => 4094487 [patent_doc_number] => 06096595 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Integration of a salicide process for MOS logic devices, and a self-aligned contact process for MOS memory devices' [patent_app_type] => 1 [patent_app_number] => 9/310254 [patent_app_country] => US [patent_app_date] => 1999-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 4745 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 447 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/096/06096595.pdf [firstpage_image] =>[orig_patent_app_number] => 310254 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/310254
Integration of a salicide process for MOS logic devices, and a self-aligned contact process for MOS memory devices May 11, 1999 Issued
Array ( [id] => 4243917 [patent_doc_number] => 06091109 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Semiconductor device having different gate oxide thicknesses by implanting halogens in one region and nitrogen in the second region' [patent_app_type] => 1 [patent_app_number] => 9/309866 [patent_app_country] => US [patent_app_date] => 1999-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7406 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/091/06091109.pdf [firstpage_image] =>[orig_patent_app_number] => 309866 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/309866
Semiconductor device having different gate oxide thicknesses by implanting halogens in one region and nitrogen in the second region May 10, 1999 Issued
Array ( [id] => 4236236 [patent_doc_number] => 06165918 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Method for forming gate oxides of different thicknesses' [patent_app_type] => 1 [patent_app_number] => 9/306654 [patent_app_country] => US [patent_app_date] => 1999-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 20 [patent_no_of_words] => 5888 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/165/06165918.pdf [firstpage_image] =>[orig_patent_app_number] => 306654 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/306654
Method for forming gate oxides of different thicknesses May 5, 1999 Issued
Array ( [id] => 4101869 [patent_doc_number] => 06100158 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Method of manufacturing an alignment mark with an etched back dielectric layer and a transparent dielectric layer and a device region on a higher plane with a wiring layer and an isolation region' [patent_app_type] => 1 [patent_app_number] => 9/302884 [patent_app_country] => US [patent_app_date] => 1999-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2321 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100158.pdf [firstpage_image] =>[orig_patent_app_number] => 302884 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/302884
Method of manufacturing an alignment mark with an etched back dielectric layer and a transparent dielectric layer and a device region on a higher plane with a wiring layer and an isolation region Apr 29, 1999 Issued
Array ( [id] => 4357554 [patent_doc_number] => 06255122 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Amorphous dielectric capacitors on silicon' [patent_app_type] => 1 [patent_app_number] => 9/300185 [patent_app_country] => US [patent_app_date] => 1999-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3049 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255122.pdf [firstpage_image] =>[orig_patent_app_number] => 300185 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/300185
Amorphous dielectric capacitors on silicon Apr 26, 1999 Issued
Array ( [id] => 4235117 [patent_doc_number] => 06165840 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Method for fabricating a DRAM cell capacitor including forming first multilayer insulator, forming conductive plug, forming second insulator, and etching second and first insulators to form the storage node' [patent_app_type] => 1 [patent_app_number] => 9/300815 [patent_app_country] => US [patent_app_date] => 1999-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2321 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/165/06165840.pdf [firstpage_image] =>[orig_patent_app_number] => 300815 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/300815
Method for fabricating a DRAM cell capacitor including forming first multilayer insulator, forming conductive plug, forming second insulator, and etching second and first insulators to form the storage node Apr 26, 1999 Issued
09/293763 SEMICONDUCTOR NONVOLATILE MEMORY DEVICE AND METHOD OF PRODUCING THE SAME Apr 18, 1999 Abandoned
Array ( [id] => 4405000 [patent_doc_number] => 06232148 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Method and apparatus leads-between-chips' [patent_app_type] => 1 [patent_app_number] => 9/290733 [patent_app_country] => US [patent_app_date] => 1999-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5027 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232148.pdf [firstpage_image] =>[orig_patent_app_number] => 290733 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/290733
Method and apparatus leads-between-chips Apr 12, 1999 Issued
Array ( [id] => 4368721 [patent_doc_number] => 06287918 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Process for fabricating a metal semiconductor device component by lateral oxidization' [patent_app_type] => 1 [patent_app_number] => 9/290086 [patent_app_country] => US [patent_app_date] => 1999-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2397 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287918.pdf [firstpage_image] =>[orig_patent_app_number] => 290086 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/290086
Process for fabricating a metal semiconductor device component by lateral oxidization Apr 11, 1999 Issued
Array ( [id] => 5801634 [patent_doc_number] => 20020009855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-24 [patent_title] => 'GATE INSULATOR PROCESS FOR NANOMETER MOSFETS' [patent_app_type] => new [patent_app_number] => 09/287976 [patent_app_country] => US [patent_app_date] => 1999-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6499 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20020009855.pdf [firstpage_image] =>[orig_patent_app_number] => 09287976 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/287976
Gate insulator process for nanometer MOSFETS Apr 6, 1999 Issued
Array ( [id] => 4366098 [patent_doc_number] => 06274440 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Manufacturing of cavity fuses on gate conductor level' [patent_app_type] => 1 [patent_app_number] => 9/282134 [patent_app_country] => US [patent_app_date] => 1999-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2689 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274440.pdf [firstpage_image] =>[orig_patent_app_number] => 282134 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/282134
Manufacturing of cavity fuses on gate conductor level Mar 30, 1999 Issued
Array ( [id] => 1549557 [patent_doc_number] => 06346424 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Process for producing high-epsilon dielectric layer or ferroelectric layer' [patent_app_type] => B1 [patent_app_number] => 09/282094 [patent_app_country] => US [patent_app_date] => 1999-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1963 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/346/06346424.pdf [firstpage_image] =>[orig_patent_app_number] => 09282094 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/282094
Process for producing high-epsilon dielectric layer or ferroelectric layer Mar 29, 1999 Issued
Array ( [id] => 4238014 [patent_doc_number] => 06080622 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Method for fabricating a DRAM cell capacitor including forming a conductive storage node by depositing and etching an insulative layer, filling with conductive material, and removing the insulative layer' [patent_app_type] => 1 [patent_app_number] => 9/281575 [patent_app_country] => US [patent_app_date] => 1999-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2104 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/080/06080622.pdf [firstpage_image] =>[orig_patent_app_number] => 281575 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/281575
Method for fabricating a DRAM cell capacitor including forming a conductive storage node by depositing and etching an insulative layer, filling with conductive material, and removing the insulative layer Mar 29, 1999 Issued
Array ( [id] => 4407151 [patent_doc_number] => 06238977 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Method for fabricating a nonvolatile memory including implanting the source region, forming the first spacers, implanting the drain regions, forming the second spacers, and forming a source line on the source and second spacers' [patent_app_type] => 1 [patent_app_number] => 9/282015 [patent_app_country] => US [patent_app_date] => 1999-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2633 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/238/06238977.pdf [firstpage_image] =>[orig_patent_app_number] => 282015 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/282015
Method for fabricating a nonvolatile memory including implanting the source region, forming the first spacers, implanting the drain regions, forming the second spacers, and forming a source line on the source and second spacers Mar 28, 1999 Issued
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