Search

William M. Brewster

Examiner (ID: 3831)

Most Active Art Unit
2823
Art Unit(s)
3716, CSDE, 2823
Total Applications
771
Issued Applications
677
Pending Applications
8
Abandoned Applications
86

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4083968 [patent_doc_number] => 06162691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Method for forming a MOSFET with raised source and drain, saliciding, and removing upper portion of gate spacers if bridging occurs' [patent_app_type] => 1 [patent_app_number] => 9/282066 [patent_app_country] => US [patent_app_date] => 1999-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2560 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/162/06162691.pdf [firstpage_image] =>[orig_patent_app_number] => 282066 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/282066
Method for forming a MOSFET with raised source and drain, saliciding, and removing upper portion of gate spacers if bridging occurs Mar 28, 1999 Issued
Array ( [id] => 4246491 [patent_doc_number] => 06136696 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Method of forming a semiconductor device with a conductor plug including five dielectric layers, the fourth dielectric layer forming sidewall spacers' [patent_app_type] => 1 [patent_app_number] => 9/277933 [patent_app_country] => US [patent_app_date] => 1999-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 8262 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/136/06136696.pdf [firstpage_image] =>[orig_patent_app_number] => 277933 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/277933
Method of forming a semiconductor device with a conductor plug including five dielectric layers, the fourth dielectric layer forming sidewall spacers Mar 28, 1999 Issued
Array ( [id] => 4131217 [patent_doc_number] => 06121096 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Implant process utilizing as an implant mask, spacers projecting vertically beyond a patterned polysilicon gate layer' [patent_app_type] => 1 [patent_app_number] => 9/270704 [patent_app_country] => US [patent_app_date] => 1999-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2775 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121096.pdf [firstpage_image] =>[orig_patent_app_number] => 270704 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/270704
Implant process utilizing as an implant mask, spacers projecting vertically beyond a patterned polysilicon gate layer Mar 16, 1999 Issued
Array ( [id] => 4247049 [patent_doc_number] => 06221728 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Semiconductor device manufacturing method' [patent_app_type] => 1 [patent_app_number] => 9/265345 [patent_app_country] => US [patent_app_date] => 1999-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 2794 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/221/06221728.pdf [firstpage_image] =>[orig_patent_app_number] => 265345 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/265345
Semiconductor device manufacturing method Mar 8, 1999 Issued
Array ( [id] => 4116811 [patent_doc_number] => 06071787 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Method of forming a capacitor including forming a first and second conductive layers and etching layers to form alloyed conductive sidewall spacers' [patent_app_type] => 1 [patent_app_number] => 9/261206 [patent_app_country] => US [patent_app_date] => 1999-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2336 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/071/06071787.pdf [firstpage_image] =>[orig_patent_app_number] => 261206 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/261206
Method of forming a capacitor including forming a first and second conductive layers and etching layers to form alloyed conductive sidewall spacers Mar 2, 1999 Issued
Array ( [id] => 4235210 [patent_doc_number] => 06165846 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Method of eliminating gate leakage in nitrogen annealed oxides' [patent_app_type] => 1 [patent_app_number] => 9/260913 [patent_app_country] => US [patent_app_date] => 1999-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 4225 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/165/06165846.pdf [firstpage_image] =>[orig_patent_app_number] => 260913 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/260913
Method of eliminating gate leakage in nitrogen annealed oxides Mar 1, 1999 Issued
Array ( [id] => 1021370 [patent_doc_number] => 06887723 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-03 [patent_title] => 'Method for processing an integrated circuit including placing dice into a carrier and testing' [patent_app_type] => utility [patent_app_number] => 09/260794 [patent_app_country] => US [patent_app_date] => 1999-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 29 [patent_no_of_words] => 7787 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/887/06887723.pdf [firstpage_image] =>[orig_patent_app_number] => 09260794 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/260794
Method for processing an integrated circuit including placing dice into a carrier and testing Feb 28, 1999 Issued
Array ( [id] => 4099724 [patent_doc_number] => 06066521 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Method for manufacturing BiMOS device with improvement of high frequency characteristics of bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 9/256173 [patent_app_country] => US [patent_app_date] => 1999-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 38 [patent_no_of_words] => 5815 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/066/06066521.pdf [firstpage_image] =>[orig_patent_app_number] => 256173 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/256173
Method for manufacturing BiMOS device with improvement of high frequency characteristics of bipolar transistor Feb 23, 1999 Issued
Array ( [id] => 4312431 [patent_doc_number] => 06242310 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Method of forming buried-strap with reduced outdiffusion including removing a sacrificial insulator leaving a gap and supporting spacer' [patent_app_type] => 1 [patent_app_number] => 9/255534 [patent_app_country] => US [patent_app_date] => 1999-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 3330 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/242/06242310.pdf [firstpage_image] =>[orig_patent_app_number] => 255534 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/255534
Method of forming buried-strap with reduced outdiffusion including removing a sacrificial insulator leaving a gap and supporting spacer Feb 21, 1999 Issued
Array ( [id] => 4382258 [patent_doc_number] => 06261978 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Process for forming semiconductor device with thick and thin films' [patent_app_type] => 1 [patent_app_number] => 9/253875 [patent_app_country] => US [patent_app_date] => 1999-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3382 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261978.pdf [firstpage_image] =>[orig_patent_app_number] => 253875 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/253875
Process for forming semiconductor device with thick and thin films Feb 21, 1999 Issued
Array ( [id] => 4168969 [patent_doc_number] => 06140177 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Process of forming a semiconductor capacitor including forming a hemispherical grain statistical mask with silicon and germanium' [patent_app_type] => 1 [patent_app_number] => 9/242153 [patent_app_country] => US [patent_app_date] => 1999-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3284 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140177.pdf [firstpage_image] =>[orig_patent_app_number] => 242153 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/242153
Process of forming a semiconductor capacitor including forming a hemispherical grain statistical mask with silicon and germanium Feb 8, 1999 Issued
Array ( [id] => 4275369 [patent_doc_number] => 06281075 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Method of controlling of floating gate oxide growth by use of an oxygen barrier' [patent_app_type] => 1 [patent_app_number] => 9/239073 [patent_app_country] => US [patent_app_date] => 1999-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 5202 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281075.pdf [firstpage_image] =>[orig_patent_app_number] => 239073 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/239073
Method of controlling of floating gate oxide growth by use of an oxygen barrier Jan 26, 1999 Issued
Array ( [id] => 4107551 [patent_doc_number] => 06057204 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Method of making a noise-isolated buried resistor by implanting a first well with a mask and then implanting an opposite conductivity well with a larger opening in the mask' [patent_app_type] => 1 [patent_app_number] => 9/229334 [patent_app_country] => US [patent_app_date] => 1999-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1391 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057204.pdf [firstpage_image] =>[orig_patent_app_number] => 229334 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/229334
Method of making a noise-isolated buried resistor by implanting a first well with a mask and then implanting an opposite conductivity well with a larger opening in the mask Jan 12, 1999 Issued
Array ( [id] => 4348233 [patent_doc_number] => 06214701 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Semiconductor substrate and thin film semiconductor device, method of manufacturing the same, and anodizing apparatus' [patent_app_type] => 1 [patent_app_number] => 9/215314 [patent_app_country] => US [patent_app_date] => 1998-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 6685 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/214/06214701.pdf [firstpage_image] =>[orig_patent_app_number] => 215314 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/215314
Semiconductor substrate and thin film semiconductor device, method of manufacturing the same, and anodizing apparatus Dec 17, 1998 Issued
Array ( [id] => 4390025 [patent_doc_number] => 06170815 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Method of fabricating a thin film transistor including forming a trench and forming a gate electrode on one side of the interior of the trench' [patent_app_type] => 1 [patent_app_number] => 9/210774 [patent_app_country] => US [patent_app_date] => 1998-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 1951 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/170/06170815.pdf [firstpage_image] =>[orig_patent_app_number] => 210774 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/210774
Method of fabricating a thin film transistor including forming a trench and forming a gate electrode on one side of the interior of the trench Dec 13, 1998 Issued
Array ( [id] => 4169106 [patent_doc_number] => 06140187 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Process for forming metal oxide semiconductors including an in situ furnace gate stack with varying silicon nitride deposition rate' [patent_app_type] => 1 [patent_app_number] => 9/205414 [patent_app_country] => US [patent_app_date] => 1998-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2542 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140187.pdf [firstpage_image] =>[orig_patent_app_number] => 205414 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/205414
Process for forming metal oxide semiconductors including an in situ furnace gate stack with varying silicon nitride deposition rate Dec 1, 1998 Issued
Array ( [id] => 4084014 [patent_doc_number] => 06162694 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Method of forming a metal gate electrode using replaced polysilicon structure' [patent_app_type] => 1 [patent_app_number] => 9/199674 [patent_app_country] => US [patent_app_date] => 1998-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2486 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/162/06162694.pdf [firstpage_image] =>[orig_patent_app_number] => 199674 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/199674
Method of forming a metal gate electrode using replaced polysilicon structure Nov 24, 1998 Issued
Array ( [id] => 4364321 [patent_doc_number] => 06191445 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Nonvolatile semiconductor memory device and method of reading a data therefrom' [patent_app_type] => 1 [patent_app_number] => 9/185580 [patent_app_country] => US [patent_app_date] => 1998-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 20405 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191445.pdf [firstpage_image] =>[orig_patent_app_number] => 185580 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/185580
Nonvolatile semiconductor memory device and method of reading a data therefrom Nov 3, 1998 Issued
Array ( [id] => 4347171 [patent_doc_number] => 06214631 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Method for patterning light emitting devices incorporating a movable mask' [patent_app_type] => 1 [patent_app_number] => 9/182636 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8235 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/214/06214631.pdf [firstpage_image] =>[orig_patent_app_number] => 182636 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/182636
Method for patterning light emitting devices incorporating a movable mask Oct 29, 1998 Issued
Array ( [id] => 4170477 [patent_doc_number] => 06036734 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Forming solid electrolyte capacitor with apparatus that vibrates capacitor element while coating with silver paste' [patent_app_type] => 1 [patent_app_number] => 9/168383 [patent_app_country] => US [patent_app_date] => 1998-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5102 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/036/06036734.pdf [firstpage_image] =>[orig_patent_app_number] => 168383 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/168383
Forming solid electrolyte capacitor with apparatus that vibrates capacitor element while coating with silver paste Oct 7, 1998 Issued
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