Search

William M. Brewster

Examiner (ID: 3831)

Most Active Art Unit
2823
Art Unit(s)
3716, CSDE, 2823
Total Applications
771
Issued Applications
677
Pending Applications
8
Abandoned Applications
86

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4348373 [patent_doc_number] => 06214711 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Method of low angle, low energy physical vapor of alloys including redepositing layers of different compositions in trenches' [patent_app_type] => 1 [patent_app_number] => 9/139583 [patent_app_country] => US [patent_app_date] => 1998-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6143 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/214/06214711.pdf [firstpage_image] =>[orig_patent_app_number] => 139583 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/139583
Method of low angle, low energy physical vapor of alloys including redepositing layers of different compositions in trenches Aug 24, 1998 Issued
Array ( [id] => 4182967 [patent_doc_number] => 06159796 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Method of forming a non-volatile memory cell having a high coupling capacitance including forming an insulator mask, etching the mask, and forming a u-shaped floating gate' [patent_app_type] => 1 [patent_app_number] => 9/126174 [patent_app_country] => US [patent_app_date] => 1998-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 25 [patent_no_of_words] => 5883 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/159/06159796.pdf [firstpage_image] =>[orig_patent_app_number] => 126174 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/126174
Method of forming a non-volatile memory cell having a high coupling capacitance including forming an insulator mask, etching the mask, and forming a u-shaped floating gate Jul 29, 1998 Issued
09/124704 PROCESS AND INTEGRATED CIRCUIT FOR A MULTILEVEL MEMORY CELL WITH AN ASYMMETRIC DRAIN Jul 28, 1998 Abandoned
Array ( [id] => 4312151 [patent_doc_number] => 06242290 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Method of forming a TFT by adding a metal to a silicon film promoting crystallization, forming a mask, forming another silicon layer with group XV elements, and gettering the metal through opening in the mask' [patent_app_type] => 1 [patent_app_number] => 9/114223 [patent_app_country] => US [patent_app_date] => 1998-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 26 [patent_no_of_words] => 6105 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/242/06242290.pdf [firstpage_image] =>[orig_patent_app_number] => 114223 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/114223
Method of forming a TFT by adding a metal to a silicon film promoting crystallization, forming a mask, forming another silicon layer with group XV elements, and gettering the metal through opening in the mask Jul 12, 1998 Issued
Array ( [id] => 4294235 [patent_doc_number] => 06197685 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Method of producing multilayer wiring device with offset axises of upper and lower plugs' [patent_app_type] => 1 [patent_app_number] => 9/113370 [patent_app_country] => US [patent_app_date] => 1998-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 34 [patent_no_of_words] => 9922 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/197/06197685.pdf [firstpage_image] =>[orig_patent_app_number] => 113370 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/113370
Method of producing multilayer wiring device with offset axises of upper and lower plugs Jun 30, 1998 Issued
Array ( [id] => 4221935 [patent_doc_number] => 06111267 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'CMOS integrated circuit including forming doped wells, a layer of intrinsic silicon, a stressed silicon germanium layer where germanium is between 25 and 50%, and another intrinsic silicon layer' [patent_app_type] => 1 [patent_app_number] => 9/071153 [patent_app_country] => US [patent_app_date] => 1998-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2453 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/111/06111267.pdf [firstpage_image] =>[orig_patent_app_number] => 071153 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/071153
CMOS integrated circuit including forming doped wells, a layer of intrinsic silicon, a stressed silicon germanium layer where germanium is between 25 and 50%, and another intrinsic silicon layer May 3, 1998 Issued
Array ( [id] => 4222543 [patent_doc_number] => 06111307 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Method of making lead frame including angle iron tie bar' [patent_app_type] => 1 [patent_app_number] => 9/055637 [patent_app_country] => US [patent_app_date] => 1998-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2806 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/111/06111307.pdf [firstpage_image] =>[orig_patent_app_number] => 055637 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/055637
Method of making lead frame including angle iron tie bar Apr 5, 1998 Issued
Array ( [id] => 4094273 [patent_doc_number] => 06096584 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Silicon-on-insulator and CMOS-on-SOI double film fabrication process with a coplanar silicon and isolation layer and adding a second silicon layer on one region' [patent_app_type] => 1 [patent_app_number] => 9/038936 [patent_app_country] => US [patent_app_date] => 1998-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4586 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/096/06096584.pdf [firstpage_image] =>[orig_patent_app_number] => 038936 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/038936
Silicon-on-insulator and CMOS-on-SOI double film fabrication process with a coplanar silicon and isolation layer and adding a second silicon layer on one region Mar 11, 1998 Issued
Array ( [id] => 1403614 [patent_doc_number] => 06541823 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-01 [patent_title] => 'Semiconductor device including multiple field effect transistors and manufacturing method thereof' [patent_app_type] => B1 [patent_app_number] => 09/038020 [patent_app_country] => US [patent_app_date] => 1998-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 94 [patent_no_of_words] => 25520 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/541/06541823.pdf [firstpage_image] =>[orig_patent_app_number] => 09038020 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/038020
Semiconductor device including multiple field effect transistors and manufacturing method thereof Mar 10, 1998 Issued
Array ( [id] => 4275999 [patent_doc_number] => 06281121 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Damascene metal interconnects using highly directional deposition of barrier and/or seed layers including (III) filling metal' [patent_app_type] => 1 [patent_app_number] => 9/036127 [patent_app_country] => US [patent_app_date] => 1998-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 1756 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281121.pdf [firstpage_image] =>[orig_patent_app_number] => 036127 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/036127
Damascene metal interconnects using highly directional deposition of barrier and/or seed layers including (III) filling metal Mar 5, 1998 Issued
Array ( [id] => 4331817 [patent_doc_number] => 06329703 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Contact between a monocrystalline silicon region and a polycrystalline silicon structure and method for producing such a contact' [patent_app_type] => 1 [patent_app_number] => 9/030227 [patent_app_country] => US [patent_app_date] => 1998-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3920 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329703.pdf [firstpage_image] =>[orig_patent_app_number] => 030227 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/030227
Contact between a monocrystalline silicon region and a polycrystalline silicon structure and method for producing such a contact Feb 24, 1998 Issued
Array ( [id] => 4348047 [patent_doc_number] => 06214690 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Method of forming a semiconductor device having integrated electrode and isolation region formation' [patent_app_type] => 1 [patent_app_number] => 8/993415 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3136 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/214/06214690.pdf [firstpage_image] =>[orig_patent_app_number] => 993415 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/993415
Method of forming a semiconductor device having integrated electrode and isolation region formation Dec 17, 1997 Issued
Array ( [id] => 4084639 [patent_doc_number] => 06025234 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Method for manufacturing thick gate oxide device' [patent_app_type] => 1 [patent_app_number] => 8/992675 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1875 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/025/06025234.pdf [firstpage_image] =>[orig_patent_app_number] => 992675 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992675
Method for manufacturing thick gate oxide device Dec 16, 1997 Issued
Array ( [id] => 1306589 [patent_doc_number] => 06617211 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-09 [patent_title] => 'Method for forming a memory integrated circuit' [patent_app_type] => B1 [patent_app_number] => 08/971014 [patent_app_country] => US [patent_app_date] => 1997-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 36 [patent_no_of_words] => 4495 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/617/06617211.pdf [firstpage_image] =>[orig_patent_app_number] => 08971014 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/971014
Method for forming a memory integrated circuit Nov 13, 1997 Issued
Array ( [id] => 1241137 [patent_doc_number] => 06682960 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-27 [patent_title] => 'Method of producing semiconductor device with a thin film transistor and a photoelectric conversion element' [patent_app_type] => B1 [patent_app_number] => 08/964797 [patent_app_country] => US [patent_app_date] => 1997-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 21 [patent_no_of_words] => 4795 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/682/06682960.pdf [firstpage_image] =>[orig_patent_app_number] => 08964797 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/964797
Method of producing semiconductor device with a thin film transistor and a photoelectric conversion element Nov 4, 1997 Issued
Array ( [id] => 4417239 [patent_doc_number] => 06194283 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'High density trench fill due to new spacer fill method including isotropically etching silicon nitride spacers' [patent_app_type] => 1 [patent_app_number] => 8/959587 [patent_app_country] => US [patent_app_date] => 1997-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3278 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/194/06194283.pdf [firstpage_image] =>[orig_patent_app_number] => 959587 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/959587
High density trench fill due to new spacer fill method including isotropically etching silicon nitride spacers Oct 28, 1997 Issued
Array ( [id] => 4138871 [patent_doc_number] => 06060334 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Electrode for optical waveguide element and method of forming the same' [patent_app_type] => 1 [patent_app_number] => 8/958581 [patent_app_country] => US [patent_app_date] => 1997-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 58 [patent_no_of_words] => 4908 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060334.pdf [firstpage_image] =>[orig_patent_app_number] => 958581 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/958581
Electrode for optical waveguide element and method of forming the same Oct 27, 1997 Issued
Array ( [id] => 4080461 [patent_doc_number] => 06054329 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Method of forming an integrated circuit spiral inductor with ferromagnetic liner' [patent_app_type] => 1 [patent_app_number] => 8/949315 [patent_app_country] => US [patent_app_date] => 1997-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 5026 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/054/06054329.pdf [firstpage_image] =>[orig_patent_app_number] => 949315 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/949315
Method of forming an integrated circuit spiral inductor with ferromagnetic liner Oct 13, 1997 Issued
Array ( [id] => 4102367 [patent_doc_number] => 06051468 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Method of forming a semiconductor structure with uniform threshold voltage and punch-through tolerance' [patent_app_type] => 1 [patent_app_number] => 8/929751 [patent_app_country] => US [patent_app_date] => 1997-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 44 [patent_no_of_words] => 6344 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/051/06051468.pdf [firstpage_image] =>[orig_patent_app_number] => 929751 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/929751
Method of forming a semiconductor structure with uniform threshold voltage and punch-through tolerance Sep 14, 1997 Issued
Array ( [id] => 4236900 [patent_doc_number] => 06090658 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Method of forming a capacitor including a bottom silicon diffusion barrier layer and a top oxygen diffusion barrier layer' [patent_app_type] => 1 [patent_app_number] => 8/911374 [patent_app_country] => US [patent_app_date] => 1997-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 4280 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/090/06090658.pdf [firstpage_image] =>[orig_patent_app_number] => 911374 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/911374
Method of forming a capacitor including a bottom silicon diffusion barrier layer and a top oxygen diffusion barrier layer Aug 6, 1997 Issued
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