Search

William M. Brewster

Examiner (ID: 263)

Most Active Art Unit
2823
Art Unit(s)
2823, CSDE, 3716
Total Applications
771
Issued Applications
677
Pending Applications
8
Abandoned Applications
86

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4644294 [patent_doc_number] => 08021899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-20 [patent_title] => 'Method of manufacturing a semiconductor device including optical test pattern above a light shielding film' [patent_app_type] => utility [patent_app_number] => 12/855906 [patent_app_country] => US [patent_app_date] => 2010-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7881 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/021/08021899.pdf [firstpage_image] =>[orig_patent_app_number] => 12855906 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/855906
Method of manufacturing a semiconductor device including optical test pattern above a light shielding film Aug 12, 2010 Issued
Array ( [id] => 6185388 [patent_doc_number] => 20110124169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'METHODS OF SELECTIVELY DEPOSITING AN EPITAXIAL LAYER' [patent_app_type] => utility [patent_app_number] => 12/849387 [patent_app_country] => US [patent_app_date] => 2010-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8360 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20110124169.pdf [firstpage_image] =>[orig_patent_app_number] => 12849387 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/849387
Methods of selectively depositing an epitaxial layer Aug 2, 2010 Issued
Array ( [id] => 8618020 [patent_doc_number] => 20130023332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-24 [patent_title] => 'Method and Apparatus for Playing a Casino Poker Game Having Two Side Games' [patent_app_type] => utility [patent_app_number] => 13/639265 [patent_app_country] => US [patent_app_date] => 2010-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4511 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13639265 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/639265
Method and Apparatus for Playing a Casino Poker Game Having Two Side Games Jul 6, 2010 Abandoned
Array ( [id] => 8548223 [patent_doc_number] => 08323100 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-04 [patent_title] => 'Wagering method for games of chance including TruePlace and flat bet resolved concurrently' [patent_app_type] => utility [patent_app_number] => 12/797193 [patent_app_country] => US [patent_app_date] => 2010-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11895 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 503 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12797193 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/797193
Wagering method for games of chance including TruePlace and flat bet resolved concurrently Jun 8, 2010 Issued
Array ( [id] => 6627682 [patent_doc_number] => 20100311506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-09 [patent_title] => 'METHOD AND SYSTEM FOR RE-CONNECTING AN UNEXPECTEDLY OFF-LINE WEB-GAME' [patent_app_type] => utility [patent_app_number] => 12/796929 [patent_app_country] => US [patent_app_date] => 2010-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3019 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0311/20100311506.pdf [firstpage_image] =>[orig_patent_app_number] => 12796929 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/796929
METHOD AND SYSTEM FOR RE-CONNECTING AN UNEXPECTEDLY OFF-LINE WEB-GAME Jun 8, 2010 Abandoned
Array ( [id] => 8468883 [patent_doc_number] => 08298059 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Method, system and computer program product for creating custom tutorials based on interactive gameplay' [patent_app_type] => utility [patent_app_number] => 12/797242 [patent_app_country] => US [patent_app_date] => 2010-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4637 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12797242 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/797242
Method, system and computer program product for creating custom tutorials based on interactive gameplay Jun 8, 2010 Issued
Array ( [id] => 9073341 [patent_doc_number] => 08550916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Interactive game systems and methods including a transceiver and transponder receptor' [patent_app_type] => utility [patent_app_number] => 12/796532 [patent_app_country] => US [patent_app_date] => 2010-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 31 [patent_no_of_words] => 9648 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12796532 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/796532
Interactive game systems and methods including a transceiver and transponder receptor Jun 7, 2010 Issued
Array ( [id] => 6507430 [patent_doc_number] => 20100219461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'Structure With PN Clamp Regions Under Trenches' [patent_app_type] => utility [patent_app_number] => 12/779844 [patent_app_country] => US [patent_app_date] => 2010-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4488 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20100219461.pdf [firstpage_image] =>[orig_patent_app_number] => 12779844 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/779844
Structure with PN clamp regions under trenches May 12, 2010 Issued
Array ( [id] => 6321164 [patent_doc_number] => 20100244192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'DIELECTRIC FILM AND SEMICONDUCTOR DEVICE USING DIELECTRIC FILM' [patent_app_type] => utility [patent_app_number] => 12/760084 [patent_app_country] => US [patent_app_date] => 2010-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 14401 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20100244192.pdf [firstpage_image] =>[orig_patent_app_number] => 12760084 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/760084
Dielectric film and semiconductor device using dielectric film including hafnium, aluminum or silicon, nitrogen, and oxygen Apr 13, 2010 Issued
Array ( [id] => 6405662 [patent_doc_number] => 20100166032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'Buried Aperture Nitride Light-Emiting Device' [patent_app_type] => utility [patent_app_number] => 12/723544 [patent_app_country] => US [patent_app_date] => 2010-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2880 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20100166032.pdf [firstpage_image] =>[orig_patent_app_number] => 12723544 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/723544
Buried aperture nitride light-emitting device Mar 11, 2010 Issued
Array ( [id] => 4538256 [patent_doc_number] => 07888783 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-15 [patent_title] => 'Chip package structure and the method thereof with adhering the chips to a frame and forming UBM layers' [patent_app_type] => utility [patent_app_number] => 12/715778 [patent_app_country] => US [patent_app_date] => 2010-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 4077 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/888/07888783.pdf [firstpage_image] =>[orig_patent_app_number] => 12715778 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/715778
Chip package structure and the method thereof with adhering the chips to a frame and forming UBM layers Mar 1, 2010 Issued
Array ( [id] => 7988773 [patent_doc_number] => 08076683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-13 [patent_title] => 'Surface-textured encapsulations for use with light emitting diodes' [patent_app_type] => utility [patent_app_number] => 12/704326 [patent_app_country] => US [patent_app_date] => 2010-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3129 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/076/08076683.pdf [firstpage_image] =>[orig_patent_app_number] => 12704326 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/704326
Surface-textured encapsulations for use with light emitting diodes Feb 10, 2010 Issued
Array ( [id] => 6240294 [patent_doc_number] => 20100133662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-03 [patent_title] => 'SEMICONDUCTOR ASSEMBLIES AND METHODS OF MANUFACTURING SUCH ASSEMBLIES' [patent_app_type] => utility [patent_app_number] => 12/696182 [patent_app_country] => US [patent_app_date] => 2010-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7715 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20100133662.pdf [firstpage_image] =>[orig_patent_app_number] => 12696182 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/696182
Semiconductor assemblies and methods of manufacturing such assemblies including trenches in a molding material between semiconductor die Jan 28, 2010 Issued
Array ( [id] => 6409837 [patent_doc_number] => 20100140707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'Metal-Gated MOSFET Devices Having Scaled Gate Stack Thickness' [patent_app_type] => utility [patent_app_number] => 12/652428 [patent_app_country] => US [patent_app_date] => 2010-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7948 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20100140707.pdf [firstpage_image] =>[orig_patent_app_number] => 12652428 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/652428
Metal-gated MOSFET devices having scaled gate stack thickness including gettering species in a buried oxide Jan 4, 2010 Issued
Array ( [id] => 6448540 [patent_doc_number] => 20100105171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-29 [patent_title] => 'SEMICONDUCTOR CHIP, METHOD OF MANUFACTURING THE SEMICONDUCTOR CHIP AND SEMICONDUCTOR CHIP PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/651234 [patent_app_country] => US [patent_app_date] => 2009-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3317 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20100105171.pdf [firstpage_image] =>[orig_patent_app_number] => 12651234 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/651234
Semiconductor chip, method of manufacturing the semiconductor chip and semiconductor chip package including an inclined via hole Dec 30, 2009 Issued
Array ( [id] => 7518778 [patent_doc_number] => 07972879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-05 [patent_title] => 'Multi-level integrated photonic devices' [patent_app_type] => utility [patent_app_number] => 12/641023 [patent_app_country] => US [patent_app_date] => 2009-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4748 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/972/07972879.pdf [firstpage_image] =>[orig_patent_app_number] => 12641023 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/641023
Multi-level integrated photonic devices Dec 16, 2009 Issued
Array ( [id] => 6342658 [patent_doc_number] => 20100084759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-08 [patent_title] => 'Die Rearrangement Package Structure Using Layout Process to Form a Compliant Configuration' [patent_app_type] => utility [patent_app_number] => 12/635388 [patent_app_country] => US [patent_app_date] => 2009-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6866 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20100084759.pdf [firstpage_image] =>[orig_patent_app_number] => 12635388 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/635388
Die rearrangement package structure using layout process to form a compliant configuration Dec 9, 2009 Issued
Array ( [id] => 6359084 [patent_doc_number] => 20100078827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'MULTILAYER WIRING STRUCTURE OF SEMICONDUCTOR DEVICE, METHOD OF PRODUCING SAID MULTILAYER WIRING STRUCTURE AND SEMICONDUCTOR DEVICE TO BE USED FOR RELIABILITY EVALUATION' [patent_app_type] => utility [patent_app_number] => 12/631592 [patent_app_country] => US [patent_app_date] => 2009-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9959 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20100078827.pdf [firstpage_image] =>[orig_patent_app_number] => 12631592 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/631592
Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation Dec 3, 2009 Issued
Array ( [id] => 6433174 [patent_doc_number] => 20100187672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-29 [patent_title] => 'ELECTRONIC APPARATUS AND CIRCUIT BOARD' [patent_app_type] => utility [patent_app_number] => 12/622193 [patent_app_country] => US [patent_app_date] => 2009-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4484 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20100187672.pdf [firstpage_image] =>[orig_patent_app_number] => 12622193 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/622193
ELECTRONIC APPARATUS AND CIRCUIT BOARD Nov 18, 2009 Abandoned
Array ( [id] => 6459298 [patent_doc_number] => 20100039847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => 'METHOD OF MANUFACTURING A SINGLE CHIP SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING A MASK ROM IN A SHORT TIME' [patent_app_type] => utility [patent_app_number] => 12/603754 [patent_app_country] => US [patent_app_date] => 2009-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 14774 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20100039847.pdf [firstpage_image] =>[orig_patent_app_number] => 12603754 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/603754
Method of manufacturing a single chip semiconductor integrated circuit device including a mask ROM in a short time Oct 21, 2009 Issued
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