Search

William M Pierce

Examiner (ID: 10512, Phone: (571)272-4414 , Office: P/3711 )

Most Active Art Unit
3711
Art Unit(s)
3711, 3304
Total Applications
2343
Issued Applications
1366
Pending Applications
134
Abandoned Applications
843

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16515995 [patent_doc_number] => 20200395253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE WITH RECESSED SPACER [patent_app_type] => utility [patent_app_number] => 17/006130 [patent_app_country] => US [patent_app_date] => 2020-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10528 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17006130 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/006130
Semiconductor device structure with recessed spacer Aug 27, 2020 Issued
Array ( [id] => 17431997 [patent_doc_number] => 20220059706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => Single Sided Channel Mesa Power Junction Field Effect Transistor [patent_app_type] => utility [patent_app_number] => 16/999942 [patent_app_country] => US [patent_app_date] => 2020-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9682 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16999942 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/999942
Single sided channel mesa power junction field effect transistor Aug 20, 2020 Issued
Array ( [id] => 17908687 [patent_doc_number] => 11462550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => SRAM structure [patent_app_type] => utility [patent_app_number] => 16/994900 [patent_app_country] => US [patent_app_date] => 2020-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7383 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16994900 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/994900
SRAM structure Aug 16, 2020 Issued
Array ( [id] => 18723330 [patent_doc_number] => 11800708 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Nonvolatile memory device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 16/995057 [patent_app_country] => US [patent_app_date] => 2020-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 10938 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16995057 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/995057
Nonvolatile memory device and method for fabricating the same Aug 16, 2020 Issued
Array ( [id] => 19444634 [patent_doc_number] => 12094926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Sidewall dopant shielding methods and approaches for trenched semiconductor device structures [patent_app_type] => utility [patent_app_number] => 16/993680 [patent_app_country] => US [patent_app_date] => 2020-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 55 [patent_no_of_words] => 12710 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16993680 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/993680
Sidewall dopant shielding methods and approaches for trenched semiconductor device structures Aug 13, 2020 Issued
Array ( [id] => 16471622 [patent_doc_number] => 20200373160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => METHOD FOR FORMING SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/988635 [patent_app_country] => US [patent_app_date] => 2020-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13239 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16988635 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/988635
Method for forming semiconductor structure Aug 7, 2020 Issued
Array ( [id] => 17730954 [patent_doc_number] => 11387356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-12 [patent_title] => Semiconductor structure and high-electron mobility transistor device having the same [patent_app_type] => utility [patent_app_number] => 16/944784 [patent_app_country] => US [patent_app_date] => 2020-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 9543 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16944784 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/944784
Semiconductor structure and high-electron mobility transistor device having the same Jul 30, 2020 Issued
Array ( [id] => 16440483 [patent_doc_number] => 20200357810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/943498 [patent_app_country] => US [patent_app_date] => 2020-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15173 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16943498 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/943498
Semiconductor memory device Jul 29, 2020 Issued
Array ( [id] => 17339492 [patent_doc_number] => 20220005823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells [patent_app_type] => utility [patent_app_number] => 16/918392 [patent_app_country] => US [patent_app_date] => 2020-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7094 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16918392 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/918392
Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells Jun 30, 2020 Issued
Array ( [id] => 16487942 [patent_doc_number] => 20200381551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/886198 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11488 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16886198 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/886198
Semiconductor device with contact plugs May 27, 2020 Issued
Array ( [id] => 16301259 [patent_doc_number] => 20200286982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => METHOD OF PROVIDING PARTIAL ELECTRICAL SHIELDING [patent_app_type] => utility [patent_app_number] => 16/881954 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6913 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16881954 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/881954
Method of providing partial electrical shielding May 21, 2020 Issued
Array ( [id] => 17723531 [patent_doc_number] => 20220216253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => CAPACITANCE MATCHED METAL WIRINGS IN DUAL CONVERSION GAIN PIXELS [patent_app_type] => utility [patent_app_number] => 17/610264 [patent_app_country] => US [patent_app_date] => 2020-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11372 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17610264 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/610264
CAPACITANCE MATCHED METAL WIRINGS IN DUAL CONVERSION GAIN PIXELS May 20, 2020 Pending
Array ( [id] => 16456394 [patent_doc_number] => 20200365820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => ORGANIC EL ELEMENT, ORGANIC EL DISPLAY PANEL, AND MANUFACTURING METHOD OF ORGANIC EL ELEMENT [patent_app_type] => utility [patent_app_number] => 16/874791 [patent_app_country] => US [patent_app_date] => 2020-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11986 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16874791 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/874791
ORGANIC EL ELEMENT, ORGANIC EL DISPLAY PANEL, AND MANUFACTURING METHOD OF ORGANIC EL ELEMENT May 14, 2020 Abandoned
Array ( [id] => 17232535 [patent_doc_number] => 20210359092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => LAYOUT TECHNIQUES AND OPTIMIZATION FOR POWER TRANSISTORS [patent_app_type] => utility [patent_app_number] => 16/874098 [patent_app_country] => US [patent_app_date] => 2020-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7470 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16874098 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/874098
Layout techniques and optimization for power transistors May 13, 2020 Issued
Array ( [id] => 16456306 [patent_doc_number] => 20200365732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => FIELD EFFECT TRANSISTOR [patent_app_type] => utility [patent_app_number] => 16/874033 [patent_app_country] => US [patent_app_date] => 2020-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5103 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16874033 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/874033
Field effect transistor May 13, 2020 Issued
Array ( [id] => 17217962 [patent_doc_number] => 20210351300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH VERTICAL SIDEWALLS [patent_app_type] => utility [patent_app_number] => 16/868828 [patent_app_country] => US [patent_app_date] => 2020-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12415 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16868828 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/868828
SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH VERTICAL SIDEWALLS May 6, 2020 Pending
Array ( [id] => 17847981 [patent_doc_number] => 11437367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => Heterogeneous integrated wideband high electron mobility transistor power amplifier with a single-crystal acoustic resonator/filter [patent_app_type] => utility [patent_app_number] => 16/854313 [patent_app_country] => US [patent_app_date] => 2020-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 8816 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16854313 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/854313
Heterogeneous integrated wideband high electron mobility transistor power amplifier with a single-crystal acoustic resonator/filter Apr 20, 2020 Issued
Array ( [id] => 17551764 [patent_doc_number] => 20220123106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/766710 [patent_app_country] => US [patent_app_date] => 2020-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7557 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16766710 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/766710
III-nitride semiconductor device with non-active regions to shape 2DEG layer Apr 12, 2020 Issued
Array ( [id] => 16566985 [patent_doc_number] => 10892362 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-01-12 [patent_title] => Devices for LDMOS and other MOS transistors with hybrid contact [patent_app_type] => utility [patent_app_number] => 16/845666 [patent_app_country] => US [patent_app_date] => 2020-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 29 [patent_no_of_words] => 10252 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16845666 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/845666
Devices for LDMOS and other MOS transistors with hybrid contact Apr 9, 2020 Issued
Array ( [id] => 16348328 [patent_doc_number] => 20200312979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => Silicon Carbide Device with Trench Gate Structure and Method of Manufacturing [patent_app_type] => utility [patent_app_number] => 16/832653 [patent_app_country] => US [patent_app_date] => 2020-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12283 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16832653 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/832653
Silicon carbide device with trench gate structure and method of manufacturing Mar 26, 2020 Issued
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