
William M. Treat
Examiner (ID: 16215)
| Most Active Art Unit | 2183 |
| Art Unit(s) | 2315, 2783, 2302, 2784, 2181, 2183 |
| Total Applications | 967 |
| Issued Applications | 755 |
| Pending Applications | 33 |
| Abandoned Applications | 179 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8260005
[patent_doc_number] => 08209518
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[patent_kind] => B2
[patent_issue_date] => 2012-06-26
[patent_title] => 'Processing bypass directory tracking system and method'
[patent_app_type] => utility
[patent_app_number] => 13/073895
[patent_app_country] => US
[patent_app_date] => 2011-03-28
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13073895
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/073895 | Processing bypass directory tracking system and method | Mar 27, 2011 | Issued |
Array
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[patent_doc_number] => 08082429
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[patent_kind] => B2
[patent_issue_date] => 2011-12-20
[patent_title] => 'Information processing apparatus and exception control circuit'
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[patent_app_date] => 2011-03-21
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/052281 | Information processing apparatus and exception control circuit | Mar 20, 2011 | Issued |
Array
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[patent_kind] => A1
[patent_issue_date] => 2011-06-02
[patent_title] => 'APPARATUS AND METHOD FOR USING BRANCH PREDICTION HEURISTICS FOR DETERMINATION OF TRACE FORMATION READINESS'
[patent_app_type] => utility
[patent_app_number] => 13/016144
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[patent_app_date] => 2011-01-28
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[pdf_file] => publications/A1/0131/20110131394.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/016144 | Apparatus and method for using branch prediction heuristics for determination of trace formation readiness | Jan 27, 2011 | Issued |
Array
(
[id] => 7682588
[patent_doc_number] => 20100241823
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[patent_kind] => A1
[patent_issue_date] => 2010-09-23
[patent_title] => 'DATA PROCESSING DEVICE AND METHOD'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/791322 | DATA PROCESSING DEVICE AND METHOD | May 31, 2010 | Abandoned |
Array
(
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[patent_title] => 'Computer Configuration Virtual Topology Discovery and Instruction Therefore'
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Array
(
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[patent_issue_date] => 2011-07-12
[patent_title] => 'Method and apparatus for matrix decompositions in programmable logic devices'
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Array
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[patent_title] => 'Computer memory architecture for hybrid serial and parallel computing systems'
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Array
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[patent_issue_date] => 2010-07-08
[patent_title] => 'PROCESSOR ARCHITECTURES FOR ENHANCED COMPUTATIONAL CAPABILITY AND LOW LATENCY'
[patent_app_type] => utility
[patent_app_number] => 12/701090
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/701090 | Processor architectures for enhanced computational capability and low latency | Feb 4, 2010 | Issued |
Array
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[id] => 4532878
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[patent_title] => 'Branch predicting apparatus and branch predicting method'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/656111 | Branch predicting apparatus and branch predicting method | Jan 14, 2010 | Issued |
Array
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[id] => 4522339
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[patent_title] => 'Latency tolerant pipeline synchronization'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/614236 | Latency tolerant pipeline synchronization | Nov 5, 2009 | Issued |
Array
(
[id] => 4549311
[patent_doc_number] => 07925867
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[patent_title] => 'Pre-decode checking for pre-decoded instructions that cross cache line boundaries'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/458512 | Pre-decode checking for pre-decoded instructions that cross cache line boundaries | Jul 13, 2009 | Issued |
Array
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Array
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Array
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[patent_title] => 'Apparatus and method for fast correct resolution of call and return instructions using multiple call/return stacks in the presence of speculative conditional instruction execution in a pipelined microprocessor'
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Array
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Array
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[patent_title] => 'PIPELINED MICROPROCESSOR WITH FAST NON-SELECTIVE CORRECT CONDITIONAL BRANCH INSTRUCTION RESOLUTION'
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Array
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