Search

William M. Treat

Examiner (ID: 16215)

Most Active Art Unit
2183
Art Unit(s)
2315, 2783, 2302, 2784, 2181, 2183
Total Applications
967
Issued Applications
755
Pending Applications
33
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 392852 [patent_doc_number] => 07302555 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-27 [patent_title] => 'Zero overhead branching and looping in time stationary processors' [patent_app_type] => utility [patent_app_number] => 10/554621 [patent_app_country] => US [patent_app_date] => 2004-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 8648 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/302/07302555.pdf [firstpage_image] =>[orig_patent_app_number] => 10554621 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/554621
Zero overhead branching and looping in time stationary processors Apr 26, 2004 Issued
Array ( [id] => 5761733 [patent_doc_number] => 20060212678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-21 [patent_title] => 'Reconfigurable processor array exploiting ilp and tlp' [patent_app_type] => utility [patent_app_number] => 10/552807 [patent_app_country] => US [patent_app_date] => 2004-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4826 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20060212678.pdf [firstpage_image] =>[orig_patent_app_number] => 10552807 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/552807
Reconfigurable processor array exploiting ilp and tlp Apr 7, 2004 Abandoned
Array ( [id] => 905032 [patent_doc_number] => 07340628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-04 [patent_title] => 'Branch based activity monitoring' [patent_app_type] => utility [patent_app_number] => 10/550335 [patent_app_country] => US [patent_app_date] => 2004-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4844 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/340/07340628.pdf [firstpage_image] =>[orig_patent_app_number] => 10550335 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/550335
Branch based activity monitoring Mar 21, 2004 Issued
Array ( [id] => 7458574 [patent_doc_number] => 20040187132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-23 [patent_title] => 'Method and apparatus for improving dispersal performance in a processor through the use of no-op ports' [patent_app_type] => new [patent_app_number] => 10/804865 [patent_app_country] => US [patent_app_date] => 2004-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2046 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20040187132.pdf [firstpage_image] =>[orig_patent_app_number] => 10804865 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/804865
Method and apparatus for improving dispersal performance in a processor through the use of no-op ports Mar 18, 2004 Issued
Array ( [id] => 992713 [patent_doc_number] => 06920551 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-07-19 [patent_title] => 'Configurable processor system' [patent_app_type] => utility [patent_app_number] => 10/805116 [patent_app_country] => US [patent_app_date] => 2004-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1877 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/920/06920551.pdf [firstpage_image] =>[orig_patent_app_number] => 10805116 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/805116
Configurable processor system Mar 18, 2004 Issued
Array ( [id] => 7154301 [patent_doc_number] => 20040172522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-02 [patent_title] => 'Floating point unit pipeline synchronized with processor pipeline' [patent_app_type] => new [patent_app_number] => 10/796552 [patent_app_country] => US [patent_app_date] => 2004-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 15257 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20040172522.pdf [firstpage_image] =>[orig_patent_app_number] => 10796552 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/796552
Floating point unit pipeline synchronized with processor pipeline Mar 7, 2004 Issued
Array ( [id] => 4606354 [patent_doc_number] => 07987340 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-26 [patent_title] => 'Communications in a processor array' [patent_app_type] => utility [patent_app_number] => 10/546616 [patent_app_country] => US [patent_app_date] => 2004-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3510 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/987/07987340.pdf [firstpage_image] =>[orig_patent_app_number] => 10546616 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/546616
Communications in a processor array Feb 18, 2004 Issued
Array ( [id] => 5001430 [patent_doc_number] => 20070044064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Processor network' [patent_app_type] => utility [patent_app_number] => 10/546615 [patent_app_country] => US [patent_app_date] => 2004-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4769 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20070044064.pdf [firstpage_image] =>[orig_patent_app_number] => 10546615 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/546615
Processor network Feb 18, 2004 Abandoned
Array ( [id] => 7676205 [patent_doc_number] => 20040153622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Instruction control device and method therefor' [patent_app_type] => new [patent_app_number] => 10/747286 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 55 [patent_no_of_words] => 15662 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20040153622.pdf [firstpage_image] =>[orig_patent_app_number] => 10747286 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/747286
Instruction control device and method therefor Dec 29, 2003 Issued
Array ( [id] => 423674 [patent_doc_number] => 07275146 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-25 [patent_title] => 'Instruction control device and method therefor' [patent_app_type] => utility [patent_app_number] => 10/747138 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 69 [patent_no_of_words] => 15415 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/275/07275146.pdf [firstpage_image] =>[orig_patent_app_number] => 10747138 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/747138
Instruction control device and method therefor Dec 29, 2003 Issued
Array ( [id] => 379020 [patent_doc_number] => 07313674 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'Instruction control device and method therefor' [patent_app_type] => utility [patent_app_number] => 10/747291 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 69 [patent_no_of_words] => 15429 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/313/07313674.pdf [firstpage_image] =>[orig_patent_app_number] => 10747291 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/747291
Instruction control device and method therefor Dec 29, 2003 Issued
Array ( [id] => 6999652 [patent_doc_number] => 20050138328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Across-thread out of order instruction dispatch in a multithreaded graphics processor' [patent_app_type] => utility [patent_app_number] => 10/742514 [patent_app_country] => US [patent_app_date] => 2003-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9296 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20050138328.pdf [firstpage_image] =>[orig_patent_app_number] => 10742514 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/742514
Across-thread out of order instruction dispatch in a multithreaded graphics processor Dec 17, 2003 Issued
Array ( [id] => 629866 [patent_doc_number] => 07136992 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-14 [patent_title] => 'Method and apparatus for a stew-based loop predictor' [patent_app_type] => utility [patent_app_number] => 10/739689 [patent_app_country] => US [patent_app_date] => 2003-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4823 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/136/07136992.pdf [firstpage_image] =>[orig_patent_app_number] => 10739689 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/739689
Method and apparatus for a stew-based loop predictor Dec 16, 2003 Issued
Array ( [id] => 706777 [patent_doc_number] => 07065635 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-06-20 [patent_title] => 'Method for handling condition code modifiers in an out-of-order multi-issue multi-stranded processor' [patent_app_type] => utility [patent_app_number] => 10/738576 [patent_app_country] => US [patent_app_date] => 2003-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4064 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/065/07065635.pdf [firstpage_image] =>[orig_patent_app_number] => 10738576 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/738576
Method for handling condition code modifiers in an out-of-order multi-issue multi-stranded processor Dec 16, 2003 Issued
Array ( [id] => 6999659 [patent_doc_number] => 20050138332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Method and apparatus for results speculation under run-ahead execution' [patent_app_type] => utility [patent_app_number] => 10/739686 [patent_app_country] => US [patent_app_date] => 2003-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3632 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20050138332.pdf [firstpage_image] =>[orig_patent_app_number] => 10739686 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/739686
Method and apparatus for results speculation under run-ahead execution Dec 16, 2003 Issued
Array ( [id] => 7100340 [patent_doc_number] => 20050132174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Predicting instruction branches with independent checking predictions' [patent_app_type] => utility [patent_app_number] => 10/735675 [patent_app_country] => US [patent_app_date] => 2003-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3101 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20050132174.pdf [firstpage_image] =>[orig_patent_app_number] => 10735675 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/735675
Predicting instruction branches with independent checking predictions Dec 15, 2003 Abandoned
Array ( [id] => 796689 [patent_doc_number] => 07430612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-30 [patent_title] => 'Computing apparatus, computing program, and computing method' [patent_app_type] => utility [patent_app_number] => 10/737130 [patent_app_country] => US [patent_app_date] => 2003-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 7754 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/430/07430612.pdf [firstpage_image] =>[orig_patent_app_number] => 10737130 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/737130
Computing apparatus, computing program, and computing method Dec 14, 2003 Issued
Array ( [id] => 524731 [patent_doc_number] => 07197628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-27 [patent_title] => 'Method and apparatus for execution flow synonyms' [patent_app_type] => utility [patent_app_number] => 10/733014 [patent_app_country] => US [patent_app_date] => 2003-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4684 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/197/07197628.pdf [firstpage_image] =>[orig_patent_app_number] => 10733014 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/733014
Method and apparatus for execution flow synonyms Dec 9, 2003 Issued
Array ( [id] => 882194 [patent_doc_number] => 07360064 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-04-15 [patent_title] => 'Thread interleaving in a multithreaded embedded processor' [patent_app_type] => utility [patent_app_number] => 10/733153 [patent_app_country] => US [patent_app_date] => 2003-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6023 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/360/07360064.pdf [firstpage_image] =>[orig_patent_app_number] => 10733153 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/733153
Thread interleaving in a multithreaded embedded processor Dec 9, 2003 Issued
Array ( [id] => 7160329 [patent_doc_number] => 20050027970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Reconfigurable instruction set computing' [patent_app_type] => utility [patent_app_number] => 10/732392 [patent_app_country] => US [patent_app_date] => 2003-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7759 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20050027970.pdf [firstpage_image] =>[orig_patent_app_number] => 10732392 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/732392
Reconfigurable instruction set computing Dec 8, 2003 Issued
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