Search

William M. Treat

Examiner (ID: 16215)

Most Active Art Unit
2183
Art Unit(s)
2315, 2783, 2302, 2784, 2181, 2183
Total Applications
967
Issued Applications
755
Pending Applications
33
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 744991 [patent_doc_number] => 07036001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-25 [patent_title] => 'Vector processing system' [patent_app_type] => utility [patent_app_number] => 10/284194 [patent_app_country] => US [patent_app_date] => 2002-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4860 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/036/07036001.pdf [firstpage_image] =>[orig_patent_app_number] => 10284194 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/284194
Vector processing system Oct 30, 2002 Issued
Array ( [id] => 7214760 [patent_doc_number] => 20040088521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-06 [patent_title] => 'Vector processing system' [patent_app_type] => new [patent_app_number] => 10/284301 [patent_app_country] => US [patent_app_date] => 2002-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4542 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20040088521.pdf [firstpage_image] =>[orig_patent_app_number] => 10284301 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/284301
Vector processing system Oct 30, 2002 Issued
Array ( [id] => 794308 [patent_doc_number] => 06983358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-03 [patent_title] => 'Method and apparatus for maintaining status coherency between queue-separated functional units' [patent_app_type] => utility [patent_app_number] => 10/279213 [patent_app_country] => US [patent_app_date] => 2002-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7400 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/983/06983358.pdf [firstpage_image] =>[orig_patent_app_number] => 10279213 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/279213
Method and apparatus for maintaining status coherency between queue-separated functional units Oct 22, 2002 Issued
Array ( [id] => 721741 [patent_doc_number] => 07055022 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-30 [patent_title] => 'Paired load-branch operation for indirect near jumps' [patent_app_type] => utility [patent_app_number] => 10/279216 [patent_app_country] => US [patent_app_date] => 2002-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6119 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/055/07055022.pdf [firstpage_image] =>[orig_patent_app_number] => 10279216 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/279216
Paired load-branch operation for indirect near jumps Oct 21, 2002 Issued
Array ( [id] => 981649 [patent_doc_number] => 06931517 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-16 [patent_title] => 'Pop-compare micro instruction for repeat string operations' [patent_app_type] => utility [patent_app_number] => 10/279212 [patent_app_country] => US [patent_app_date] => 2002-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 8867 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/931/06931517.pdf [firstpage_image] =>[orig_patent_app_number] => 10279212 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/279212
Pop-compare micro instruction for repeat string operations Oct 21, 2002 Issued
Array ( [id] => 6685037 [patent_doc_number] => 20030120901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Multithreaded processor with efficient processing for convergence device applications' [patent_app_type] => new [patent_app_number] => 10/269372 [patent_app_country] => US [patent_app_date] => 2002-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3163 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20030120901.pdf [firstpage_image] =>[orig_patent_app_number] => 10269372 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/269372
Multithreaded processor with efficient processing for convergence device applications Oct 10, 2002 Issued
Array ( [id] => 987741 [patent_doc_number] => 06925551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-02 [patent_title] => 'Method, apparatus and system for accessing a global promotion facility through execution of a branch-type instruction' [patent_app_type] => utility [patent_app_number] => 10/268742 [patent_app_country] => US [patent_app_date] => 2002-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9097 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/925/06925551.pdf [firstpage_image] =>[orig_patent_app_number] => 10268742 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/268742
Method, apparatus and system for accessing a global promotion facility through execution of a branch-type instruction Oct 9, 2002 Issued
Array ( [id] => 7460291 [patent_doc_number] => 20040068638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-08 [patent_title] => 'Method, apparatus, and system for enhancing control flows in processors' [patent_app_type] => new [patent_app_number] => 10/264796 [patent_app_country] => US [patent_app_date] => 2002-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2153 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20040068638.pdf [firstpage_image] =>[orig_patent_app_number] => 10264796 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/264796
Method, apparatus, and system for enhancing control flows in processors Oct 3, 2002 Abandoned
Array ( [id] => 7460894 [patent_doc_number] => 20040068727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-08 [patent_title] => 'Method and apparatus for parallel execution of computer software using a distilled program' [patent_app_type] => new [patent_app_number] => 10/263514 [patent_app_country] => US [patent_app_date] => 2002-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6475 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20040068727.pdf [firstpage_image] =>[orig_patent_app_number] => 10263514 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/263514
Method and apparatus for parallel execution of computer software using a distilled program Oct 1, 2002 Issued
Array ( [id] => 666987 [patent_doc_number] => 07103756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Data processor with individually writable register subword locations' [patent_app_type] => utility [patent_app_number] => 10/261131 [patent_app_country] => US [patent_app_date] => 2002-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3698 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/103/07103756.pdf [firstpage_image] =>[orig_patent_app_number] => 10261131 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/261131
Data processor with individually writable register subword locations Sep 29, 2002 Issued
Array ( [id] => 1066745 [patent_doc_number] => 06851041 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-01 [patent_title] => 'Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor' [patent_app_type] => utility [patent_app_number] => 10/254012 [patent_app_country] => US [patent_app_date] => 2002-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 6827 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/851/06851041.pdf [firstpage_image] =>[orig_patent_app_number] => 10254012 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/254012
Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor Sep 23, 2002 Issued
Array ( [id] => 6675655 [patent_doc_number] => 20030061258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Method and apparatus for processing an event occurrence for at least one thread within a multithreaded processor' [patent_app_type] => new [patent_app_number] => 10/246887 [patent_app_country] => US [patent_app_date] => 2002-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 16558 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20030061258.pdf [firstpage_image] =>[orig_patent_app_number] => 10246887 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/246887
Method and apparatus for processing an event occurrence for a least one thread within a multithreaded processor Sep 17, 2002 Issued
Array ( [id] => 6831453 [patent_doc_number] => 20030182511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'Apparatus and method for resolving an instruction conflict in a software pipeline nested loop procedure in a digital signal processor' [patent_app_type] => new [patent_app_number] => 10/225035 [patent_app_country] => US [patent_app_date] => 2002-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11215 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20030182511.pdf [firstpage_image] =>[orig_patent_app_number] => 10225035 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/225035
Apparatus and method for resolving an instruction conflict in a software pipeline nested loop procedure in a digital signal processor Aug 20, 2002 Abandoned
Array ( [id] => 6554730 [patent_doc_number] => 20020194456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'System and method for register renaming' [patent_app_type] => new [patent_app_number] => 10/222935 [patent_app_country] => US [patent_app_date] => 2002-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4523 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20020194456.pdf [firstpage_image] =>[orig_patent_app_number] => 10222935 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/222935
System and method for register renaming Aug 18, 2002 Issued
Array ( [id] => 396801 [patent_doc_number] => 07299369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-20 [patent_title] => 'Power reduction in microprocessor systems' [patent_app_type] => utility [patent_app_number] => 10/486301 [patent_app_country] => US [patent_app_date] => 2002-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2520 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/299/07299369.pdf [firstpage_image] =>[orig_patent_app_number] => 10486301 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/486301
Power reduction in microprocessor systems Aug 7, 2002 Issued
Array ( [id] => 7407682 [patent_doc_number] => 20040019767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-29 [patent_title] => 'Method for quickly determining length of an execution package' [patent_app_type] => new [patent_app_number] => 10/064597 [patent_app_country] => US [patent_app_date] => 2002-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2010 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20040019767.pdf [firstpage_image] =>[orig_patent_app_number] => 10064597 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/064597
Method for quickly determining length of an execution package Jul 28, 2002 Issued
Array ( [id] => 7407684 [patent_doc_number] => 20040019768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-29 [patent_title] => 'Method and system for using dynamic, deferred operation information to control eager deferral of control-speculative loads' [patent_app_type] => new [patent_app_number] => 10/208095 [patent_app_country] => US [patent_app_date] => 2002-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8920 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20040019768.pdf [firstpage_image] =>[orig_patent_app_number] => 10208095 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/208095
Method and system for using dynamic, deferred operation information to control eager deferral of control-speculative loads Jul 28, 2002 Issued
Array ( [id] => 7611324 [patent_doc_number] => 06904518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-07 [patent_title] => 'Finding a significant bit in a computer data word' [patent_app_type] => utility [patent_app_number] => 10/202960 [patent_app_country] => US [patent_app_date] => 2002-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 859 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/904/06904518.pdf [firstpage_image] =>[orig_patent_app_number] => 10202960 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/202960
Finding a significant bit in a computer data word Jul 24, 2002 Issued
Array ( [id] => 1030611 [patent_doc_number] => 06883085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-19 [patent_title] => 'Handling of coprocessor instructions in a data processing apparatus' [patent_app_type] => utility [patent_app_number] => 10/202029 [patent_app_country] => US [patent_app_date] => 2002-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6026 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/883/06883085.pdf [firstpage_image] =>[orig_patent_app_number] => 10202029 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/202029
Handling of coprocessor instructions in a data processing apparatus Jul 24, 2002 Issued
Array ( [id] => 1030609 [patent_doc_number] => 06883084 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-19 [patent_title] => 'Reconfigurable data path processor' [patent_app_type] => utility [patent_app_number] => 10/206517 [patent_app_country] => US [patent_app_date] => 2002-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 17680 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/883/06883084.pdf [firstpage_image] =>[orig_patent_app_number] => 10206517 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/206517
Reconfigurable data path processor Jul 24, 2002 Issued
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