William M. Treat

Array ( [id] => 6451428 [patent_doc_number] => 20020129225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Processing device for executing virtual machine instructions' [patent_app_type] => new [patent_app_number] => 10/074774 [patent_app_country] => US [patent_app_date] => 2002-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8558 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20020129225.pdf [firstpage_image] =>[orig_patent_app_number] => 10074774 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6369335 [patent_doc_number] => 20020059500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-16 [patent_title] => 'Method and apparatus for handling invalidation requests to processors not present in a computer system' [patent_app_type] => new [patent_app_number] => 10/047347 [patent_app_country] => US [patent_app_date] => 2002-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2507 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20020059500.pdf [firstpage_image] =>[orig_patent_app_number] => 10047347 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6698172 [patent_doc_number] => 20030110366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'Run-ahead program execution with value prediction' [patent_app_type] => new [patent_app_number] => 10/017793 [patent_app_country] => US [patent_app_date] => 2001-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4330 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20030110366.pdf [firstpage_image] =>[orig_patent_app_number] => 10017793 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5926561 [patent_doc_number] => 20020116600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Method and apparatus for processing events in a multithreaded processor' [patent_app_type] => new [patent_app_number] => 10/006348 [patent_app_country] => US [patent_app_date] => 2001-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 15619 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20020116600.pdf [firstpage_image] =>[orig_patent_app_number] => 10006348 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1058997 [patent_doc_number] => 06857062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-15 [patent_title] => 'Broadcast state renaming in a microprocessor' [patent_app_type] => utility [patent_app_number] => 10/007151 [patent_app_country] => US [patent_app_date] => 2001-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4713 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/857/06857062.pdf [firstpage_image] =>[orig_patent_app_number] => 10007151 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 792690 [patent_doc_number] => 06986021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-10 [patent_title] => 'Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements' [patent_app_type] => utility [patent_app_number] => 09/997987 [patent_app_country] => US [patent_app_date] => 2001-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 14340 [patent_no_of_claims] => 104 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/986/06986021.pdf [firstpage_image] =>[orig_patent_app_number] => 09997987 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5937685 [patent_doc_number] => 20020062352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-23 [patent_title] => 'Multiprocessor system and control method thereof' [patent_app_type] => new [patent_app_number] => 09/989028 [patent_app_country] => US [patent_app_date] => 2001-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8748 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20020062352.pdf [firstpage_image] =>[orig_patent_app_number] => 09989028 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1011418 [patent_doc_number] => 06901507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-31 [patent_title] => 'Context scheduling' [patent_app_type] => utility [patent_app_number] => 09/989482 [patent_app_country] => US [patent_app_date] => 2001-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2975 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/901/06901507.pdf [firstpage_image] =>[orig_patent_app_number] => 09989482 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1258460 [patent_doc_number] => 06671798 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-30 [patent_title] => 'Configurable branch prediction for a processor performing speculative execution' [patent_app_type] => B1 [patent_app_number] => 09/992822 [patent_app_country] => US [patent_app_date] => 2001-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9166 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/671/06671798.pdf [firstpage_image] =>[orig_patent_app_number] => 09992822 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 992709 [patent_doc_number] => 06920550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-19 [patent_title] => 'System and method for decoding and executing program binaries' [patent_app_type] => utility [patent_app_number] => 09/999451 [patent_app_country] => US [patent_app_date] => 2001-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7873 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/920/06920550.pdf [firstpage_image] =>[orig_patent_app_number] => 09999451 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6388992 [patent_doc_number] => 20020120831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-29 [patent_title] => 'Stall control' [patent_app_type] => new [patent_app_number] => 09/992159 [patent_app_country] => US [patent_app_date] => 2001-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 11018 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20020120831.pdf [firstpage_image] =>[orig_patent_app_number] => 09992159 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7605701 [patent_doc_number] => 07100021 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-29 [patent_title] => 'Barrier synchronization mechanism for processors of a systolic array' [patent_app_type] => utility [patent_app_number] => 09/978647 [patent_app_country] => US [patent_app_date] => 2001-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9502 [patent_no_of_claims] => 80 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/100/07100021.pdf [firstpage_image] =>[orig_patent_app_number] => 09978647 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 987748 [patent_doc_number] => 06925554 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-02 [patent_title] => 'Method of programming USB microcontrollers' [patent_app_type] => utility [patent_app_number] => 09/973260 [patent_app_country] => US [patent_app_date] => 2001-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3041 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/925/06925554.pdf [firstpage_image] =>[orig_patent_app_number] => 09973260 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6211567 [patent_doc_number] => 20020073299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Methods and apparatus for scalable instruction set architecture with dynamic compact instructions' [patent_app_type] => new [patent_app_number] => 09/969077 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9494 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20020073299.pdf [firstpage_image] =>[orig_patent_app_number] => 09969077 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 690836 [patent_doc_number] => 07080238 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'Non-blocking, multi-context pipelined processor' [patent_app_type] => utility [patent_app_number] => 09/941528 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3560 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/080/07080238.pdf [firstpage_image] =>[orig_patent_app_number] => 09941528 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5890387 [patent_doc_number] => 20020013918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-31 [patent_title] => 'Devices, systems and methods for mode driven stops' [patent_app_type] => new [patent_app_number] => 09/938201 [patent_app_country] => US [patent_app_date] => 2001-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 36837 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20020013918.pdf [firstpage_image] =>[orig_patent_app_number] => 09938201 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6689783 [patent_doc_number] => 20030033509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-13 [patent_title] => 'Architectural reuse of registers for out of order simultaneous multi-threading' [patent_app_type] => new [patent_app_number] => 09/924335 [patent_app_country] => US [patent_app_date] => 2001-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3301 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20030033509.pdf [firstpage_image] =>[orig_patent_app_number] => 09924335 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1097380 [patent_doc_number] => 06826674 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-30 [patent_title] => 'Program product and data processor' [patent_app_type] => B1 [patent_app_number] => 09/830664 [patent_app_country] => US [patent_app_date] => 2001-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 11612 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/826/06826674.pdf [firstpage_image] =>[orig_patent_app_number] => 09830664 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 771403 [patent_doc_number] => 07010677 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-07 [patent_title] => 'Data processor speeding up repeat processing by inhibiting remaining instructions after a break in a repeat block' [patent_app_type] => utility [patent_app_number] => 09/921554 [patent_app_country] => US [patent_app_date] => 2001-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 36 [patent_no_of_words] => 28931 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/010/07010677.pdf [firstpage_image] =>[orig_patent_app_number] => 09921554 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7001789 [patent_doc_number] => 20010054141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-20 [patent_title] => 'Microsequencer with nested loop counters' [patent_app_type] => new [patent_app_number] => 09/912585 [patent_app_country] => US [patent_app_date] => 2001-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8070 [patent_no_of_claims] => 75 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20010054141.pdf [firstpage_image] =>[orig_patent_app_number] => 09912585 [rel_patent_id] =>[rel_patent_doc_number] =>)