William M. Treat

Array ( [id] => 1092881 [patent_doc_number] => 06829696 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-07 [patent_title] => 'Data processing system with register store/load utilizing data packing/unpacking' [patent_app_type] => B1 [patent_app_number] => 09/687540 [patent_app_country] => US [patent_app_date] => 2000-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 10569 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/829/06829696.pdf [firstpage_image] =>[orig_patent_app_number] => 09687540 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1206925 [patent_doc_number] => 06721874 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-13 [patent_title] => 'Method and system for dynamically shared completion table supporting multiple threads in a processing system' [patent_app_type] => B1 [patent_app_number] => 09/687078 [patent_app_country] => US [patent_app_date] => 2000-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6820 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/721/06721874.pdf [firstpage_image] =>[orig_patent_app_number] => 09687078 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1201047 [patent_doc_number] => 06728874 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-27 [patent_title] => 'System and method for processing vectorized data' [patent_app_type] => B1 [patent_app_number] => 09/685441 [patent_app_country] => US [patent_app_date] => 2000-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 4619 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728874.pdf [firstpage_image] =>[orig_patent_app_number] => 09685441 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7615392 [patent_doc_number] => 06948055 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-20 [patent_title] => 'Accuracy of multiple branch prediction schemes' [patent_app_type] => utility [patent_app_number] => 09/685270 [patent_app_country] => US [patent_app_date] => 2000-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3800 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/948/06948055.pdf [firstpage_image] =>[orig_patent_app_number] => 09685270 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1092879 [patent_doc_number] => 06829695 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-07 [patent_title] => 'Enhanced boolean processor with parallel input' [patent_app_type] => B1 [patent_app_number] => 09/684761 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 44 [patent_no_of_words] => 34224 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/829/06829695.pdf [firstpage_image] =>[orig_patent_app_number] => 09684761 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1186690 [patent_doc_number] => 06738897 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-18 [patent_title] => 'Incorporating local branch history when predicting multiple conditional branch outcomes' [patent_app_type] => B1 [patent_app_number] => 09/680840 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3474 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/738/06738897.pdf [firstpage_image] =>[orig_patent_app_number] => 09680840 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1201040 [patent_doc_number] => 06728870 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-27 [patent_title] => 'Register move operations' [patent_app_type] => B1 [patent_app_number] => 09/680894 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1774 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728870.pdf [firstpage_image] =>[orig_patent_app_number] => 09680894 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1169857 [patent_doc_number] => 06763450 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-13 [patent_title] => 'Processor' [patent_app_type] => B1 [patent_app_number] => 09/680609 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 15339 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/763/06763450.pdf [firstpage_image] =>[orig_patent_app_number] => 09680609 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1271960 [patent_doc_number] => 06662296 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'Method and system for testing millicode branch points' [patent_app_type] => B1 [patent_app_number] => 09/677231 [patent_app_country] => US [patent_app_date] => 2000-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2494 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/662/06662296.pdf [firstpage_image] =>[orig_patent_app_number] => 09677231 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1258436 [patent_doc_number] => 06671793 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-30 [patent_title] => 'Method and system for managing the result from a translator co-processor in a pipelined processor' [patent_app_type] => B1 [patent_app_number] => 09/678061 [patent_app_country] => US [patent_app_date] => 2000-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3180 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/671/06671793.pdf [firstpage_image] =>[orig_patent_app_number] => 09678061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1258439 [patent_doc_number] => 06671794 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-30 [patent_title] => 'Address generation interlock detection' [patent_app_type] => B1 [patent_app_number] => 09/678226 [patent_app_country] => US [patent_app_date] => 2000-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3939 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/671/06671794.pdf [firstpage_image] =>[orig_patent_app_number] => 09678226 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7962225 [patent_doc_number] => 06681317 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-20 [patent_title] => 'Method and apparatus to provide advanced load ordering' [patent_app_type] => B1 [patent_app_number] => 09/677228 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5461 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/681/06681317.pdf [firstpage_image] =>[orig_patent_app_number] => 09677228 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1155269 [patent_doc_number] => 06779103 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-17 [patent_title] => 'Control word register renaming' [patent_app_type] => B1 [patent_app_number] => 09/676550 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5493 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/779/06779103.pdf [firstpage_image] =>[orig_patent_app_number] => 09676550 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1271947 [patent_doc_number] => 06662294 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'Converting short branches to predicated instructions' [patent_app_type] => B1 [patent_app_number] => 09/671868 [patent_app_country] => US [patent_app_date] => 2000-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5759 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/662/06662294.pdf [firstpage_image] =>[orig_patent_app_number] => 09671868 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1177678 [patent_doc_number] => 06760833 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-06 [patent_title] => 'Split embedded DRAM processor' [patent_app_type] => B1 [patent_app_number] => 09/652638 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 15309 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/760/06760833.pdf [firstpage_image] =>[orig_patent_app_number] => 09652638 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1567512 [patent_doc_number] => 06363475 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Apparatus and method for program level parallelism in a VLIW processor' [patent_app_type] => B1 [patent_app_number] => 09/653641 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9714 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363475.pdf [firstpage_image] =>[orig_patent_app_number] => 09653641 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1289248 [patent_doc_number] => 06647488 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-11 [patent_title] => 'Processor' [patent_app_type] => B1 [patent_app_number] => 09/614455 [patent_app_country] => US [patent_app_date] => 2000-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 5152 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/647/06647488.pdf [firstpage_image] =>[orig_patent_app_number] => 09614455 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1124944 [patent_doc_number] => 06799265 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-28 [patent_title] => 'Dependency checking for reconfigurable logic' [patent_app_type] => B1 [patent_app_number] => 09/613498 [patent_app_country] => US [patent_app_date] => 2000-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 5340 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/799/06799265.pdf [firstpage_image] =>[orig_patent_app_number] => 09613498 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 995910 [patent_doc_number] => 06918032 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-07-12 [patent_title] => 'Hardware predication for conditional instruction path branching' [patent_app_type] => utility [patent_app_number] => 09/611282 [patent_app_country] => US [patent_app_date] => 2000-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11591 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/918/06918032.pdf [firstpage_image] =>[orig_patent_app_number] => 09611282 [rel_patent_id] =>[rel_patent_doc_number] =>)