Search

William M. Treat

Examiner (ID: 16215)

Most Active Art Unit
2183
Art Unit(s)
2315, 2783, 2302, 2784, 2181, 2183
Total Applications
967
Issued Applications
755
Pending Applications
33
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1417088 [patent_doc_number] => 06532534 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Information processing apparatus provided with branch history with plurality of designation ways' [patent_app_type] => B1 [patent_app_number] => 09/456918 [patent_app_country] => US [patent_app_date] => 1999-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 6663 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/532/06532534.pdf [firstpage_image] =>[orig_patent_app_number] => 09456918 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/456918
Information processing apparatus provided with branch history with plurality of designation ways Dec 6, 1999 Issued
Array ( [id] => 1466692 [patent_doc_number] => 06351802 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Method and apparatus for constructing a pre-scheduled instruction cache' [patent_app_type] => B1 [patent_app_number] => 09/454266 [patent_app_country] => US [patent_app_date] => 1999-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3116 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351802.pdf [firstpage_image] =>[orig_patent_app_number] => 09454266 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/454266
Method and apparatus for constructing a pre-scheduled instruction cache Dec 2, 1999 Issued
09/442874 DECOMPRESSION BIT PROCESSING WITH A GENERAL PURPOSE ALIGNMENT TOOL Nov 17, 1999 Abandoned
Array ( [id] => 1311453 [patent_doc_number] => 06625722 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Processor controller for accelerating instruction issuing rate' [patent_app_type] => B1 [patent_app_number] => 09/423917 [patent_app_country] => US [patent_app_date] => 1999-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 8733 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625722.pdf [firstpage_image] =>[orig_patent_app_number] => 09423917 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/423917
Processor controller for accelerating instruction issuing rate Nov 15, 1999 Issued
Array ( [id] => 1186393 [patent_doc_number] => 06742113 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-25 [patent_title] => 'Microprocessor with EIT, processing capability, and EIT processing method' [patent_app_type] => B1 [patent_app_number] => 09/440699 [patent_app_country] => US [patent_app_date] => 1999-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7666 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/742/06742113.pdf [firstpage_image] =>[orig_patent_app_number] => 09440699 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/440699
Microprocessor with EIT, processing capability, and EIT processing method Nov 15, 1999 Issued
Array ( [id] => 1521771 [patent_doc_number] => 06502187 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Pipeline computer dividing a variable-length data-handling instruction into fixed-length data-handling instructions' [patent_app_type] => B1 [patent_app_number] => 09/440134 [patent_app_country] => US [patent_app_date] => 1999-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4801 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502187.pdf [firstpage_image] =>[orig_patent_app_number] => 09440134 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/440134
Pipeline computer dividing a variable-length data-handling instruction into fixed-length data-handling instructions Nov 14, 1999 Issued
Array ( [id] => 1308992 [patent_doc_number] => 06629236 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Master-slave latch circuit for multithreaded processing' [patent_app_type] => B1 [patent_app_number] => 09/439581 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 65 [patent_figures_cnt] => 65 [patent_no_of_words] => 6778 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629236.pdf [firstpage_image] =>[orig_patent_app_number] => 09439581 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/439581
Master-slave latch circuit for multithreaded processing Nov 11, 1999 Issued
Array ( [id] => 1326935 [patent_doc_number] => 06609194 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-19 [patent_title] => 'Apparatus for performing branch target address calculation based on branch type' [patent_app_type] => B1 [patent_app_number] => 09/438907 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6605 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/609/06609194.pdf [firstpage_image] =>[orig_patent_app_number] => 09438907 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/438907
Apparatus for performing branch target address calculation based on branch type Nov 11, 1999 Issued
Array ( [id] => 7611327 [patent_doc_number] => 06904515 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-07 [patent_title] => 'Multi-instruction set flag preservation apparatus and method' [patent_app_type] => utility [patent_app_number] => 09/436882 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3746 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/904/06904515.pdf [firstpage_image] =>[orig_patent_app_number] => 09436882 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/436882
Multi-instruction set flag preservation apparatus and method Nov 8, 1999 Issued
Array ( [id] => 1279610 [patent_doc_number] => 06654871 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Device and a method for performing stack operations in a processing system' [patent_app_type] => B1 [patent_app_number] => 09/436891 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3280 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654871.pdf [firstpage_image] =>[orig_patent_app_number] => 09436891 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/436891
Device and a method for performing stack operations in a processing system Nov 8, 1999 Issued
Array ( [id] => 1513320 [patent_doc_number] => 06442673 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Update forwarding cache for address mode' [patent_app_type] => B1 [patent_app_number] => 09/434086 [patent_app_country] => US [patent_app_date] => 1999-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 11474 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442673.pdf [firstpage_image] =>[orig_patent_app_number] => 09434086 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/434086
Update forwarding cache for address mode Nov 4, 1999 Issued
Array ( [id] => 1584888 [patent_doc_number] => 06449710 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Stitching parcels' [patent_app_type] => B1 [patent_app_number] => 09/429053 [patent_app_country] => US [patent_app_date] => 1999-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7808 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449710.pdf [firstpage_image] =>[orig_patent_app_number] => 09429053 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/429053
Stitching parcels Oct 28, 1999 Issued
Array ( [id] => 4379873 [patent_doc_number] => 06192468 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Apparatus and method for detecting microbranches early' [patent_app_type] => 1 [patent_app_number] => 9/428591 [patent_app_country] => US [patent_app_date] => 1999-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 15703 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/192/06192468.pdf [firstpage_image] =>[orig_patent_app_number] => 428591 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/428591
Apparatus and method for detecting microbranches early Oct 26, 1999 Issued
Array ( [id] => 4312532 [patent_doc_number] => 06237089 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Method and apparatus for affecting subsequent instruction processing in a data processor' [patent_app_type] => 1 [patent_app_number] => 9/425469 [patent_app_country] => US [patent_app_date] => 1999-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4296 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/237/06237089.pdf [firstpage_image] =>[orig_patent_app_number] => 425469 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/425469
Method and apparatus for affecting subsequent instruction processing in a data processor Oct 21, 1999 Issued
Array ( [id] => 1201028 [patent_doc_number] => 06728865 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-27 [patent_title] => 'Pipeline replay support for unaligned memory operations' [patent_app_type] => B1 [patent_app_number] => 09/420748 [patent_app_country] => US [patent_app_date] => 1999-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 8910 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728865.pdf [firstpage_image] =>[orig_patent_app_number] => 09420748 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/420748
Pipeline replay support for unaligned memory operations Oct 19, 1999 Issued
Array ( [id] => 1284624 [patent_doc_number] => 06651157 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Multi-processor system and method of accessing data therein' [patent_app_type] => B1 [patent_app_number] => 09/418520 [patent_app_country] => US [patent_app_date] => 1999-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1901 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/651/06651157.pdf [firstpage_image] =>[orig_patent_app_number] => 09418520 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/418520
Multi-processor system and method of accessing data therein Oct 14, 1999 Issued
Array ( [id] => 1584901 [patent_doc_number] => 06449712 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructions' [patent_app_type] => B1 [patent_app_number] => 09/410851 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7499 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449712.pdf [firstpage_image] =>[orig_patent_app_number] => 09410851 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/410851
Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructions Sep 30, 1999 Issued
Array ( [id] => 1166278 [patent_doc_number] => 06772325 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-03 [patent_title] => 'Processor architecture and operation for exploiting improved branch control instruction' [patent_app_type] => B1 [patent_app_number] => 09/410682 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 18142 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/772/06772325.pdf [firstpage_image] =>[orig_patent_app_number] => 09410682 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/410682
Processor architecture and operation for exploiting improved branch control instruction Sep 30, 1999 Issued
Array ( [id] => 1456807 [patent_doc_number] => 06457118 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Method and system for selecting and using source operands in computer system instructions' [patent_app_type] => B1 [patent_app_number] => 09/410549 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3384 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457118.pdf [firstpage_image] =>[orig_patent_app_number] => 09410549 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/410549
Method and system for selecting and using source operands in computer system instructions Sep 30, 1999 Issued
09/410599 INSTRUCTIONS FOR MANIPULATING VECTORED DATA Sep 30, 1999 Abandoned
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