
William M. Treat
Examiner (ID: 16215)
| Most Active Art Unit | 2183 |
| Art Unit(s) | 2315, 2783, 2302, 2784, 2181, 2183 |
| Total Applications | 967 |
| Issued Applications | 755 |
| Pending Applications | 33 |
| Abandoned Applications | 179 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4426666
[patent_doc_number] => 06178499
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-23
[patent_title] => 'Interruptable multiple execution unit processing during operations utilizing multiple assignment of registers'
[patent_app_type] => 1
[patent_app_number] => 9/212143
[patent_app_country] => US
[patent_app_date] => 1998-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 5934
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/178/06178499.pdf
[firstpage_image] =>[orig_patent_app_number] => 212143
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/212143 | Interruptable multiple execution unit processing during operations utilizing multiple assignment of registers | Dec 14, 1998 | Issued |
Array
(
[id] => 4209150
[patent_doc_number] => 06154832
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-28
[patent_title] => 'Processor employing multiple register sets to eliminate interrupts'
[patent_app_type] => 1
[patent_app_number] => 9/205444
[patent_app_country] => US
[patent_app_date] => 1998-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4144
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/154/06154832.pdf
[firstpage_image] =>[orig_patent_app_number] => 205444
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/205444 | Processor employing multiple register sets to eliminate interrupts | Dec 3, 1998 | Issued |
Array
(
[id] => 4422724
[patent_doc_number] => 06173389
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-09
[patent_title] => 'Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor'
[patent_app_type] => 1
[patent_app_number] => 9/205588
[patent_app_country] => US
[patent_app_date] => 1998-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 6698
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/173/06173389.pdf
[firstpage_image] =>[orig_patent_app_number] => 205588
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/205588 | Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor | Dec 3, 1998 | Issued |
Array
(
[id] => 4352057
[patent_doc_number] => 06314509
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-06
[patent_title] => 'Efficient method for fetching instructions having a non-power of two size'
[patent_app_type] => 1
[patent_app_number] => 9/205120
[patent_app_country] => US
[patent_app_date] => 1998-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 14
[patent_no_of_words] => 7722
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/314/06314509.pdf
[firstpage_image] =>[orig_patent_app_number] => 205120
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/205120 | Efficient method for fetching instructions having a non-power of two size | Dec 2, 1998 | Issued |
Array
(
[id] => 4349967
[patent_doc_number] => 06321325
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-20
[patent_title] => 'Dual in-line buffers for an instruction fetch unit'
[patent_app_type] => 1
[patent_app_number] => 9/205121
[patent_app_country] => US
[patent_app_date] => 1998-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 14
[patent_no_of_words] => 7620
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/321/06321325.pdf
[firstpage_image] =>[orig_patent_app_number] => 205121
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/205121 | Dual in-line buffers for an instruction fetch unit | Dec 2, 1998 | Issued |
Array
(
[id] => 1466684
[patent_doc_number] => 06351800
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-26
[patent_title] => 'System and method for assisting a microprocessor'
[patent_app_type] => B1
[patent_app_number] => 09/201312
[patent_app_country] => US
[patent_app_date] => 1998-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2767
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 19
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/351/06351800.pdf
[firstpage_image] =>[orig_patent_app_number] => 09201312
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/201312 | System and method for assisting a microprocessor | Nov 28, 1998 | Issued |
Array
(
[id] => 4022323
[patent_doc_number] => 05987592
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-16
[patent_title] => 'Flexible resource access in a microprocessor'
[patent_app_type] => 1
[patent_app_number] => 9/195181
[patent_app_country] => US
[patent_app_date] => 1998-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 11493
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/987/05987592.pdf
[firstpage_image] =>[orig_patent_app_number] => 195181
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/195181 | Flexible resource access in a microprocessor | Nov 16, 1998 | Issued |
Array
(
[id] => 4101150
[patent_doc_number] => 06163837
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-19
[patent_title] => 'Writing of instruction results produced by instruction execution circuits to result destinations'
[patent_app_type] => 1
[patent_app_number] => 9/193487
[patent_app_country] => US
[patent_app_date] => 1998-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 9379
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/163/06163837.pdf
[firstpage_image] =>[orig_patent_app_number] => 193487
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/193487 | Writing of instruction results produced by instruction execution circuits to result destinations | Nov 16, 1998 | Issued |
Array
(
[id] => 3916134
[patent_doc_number] => 05951675
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-14
[patent_title] => 'Instruction alignment unit employing dual instruction queues for high frequency instruction dispatch'
[patent_app_type] => 1
[patent_app_number] => 9/179620
[patent_app_country] => US
[patent_app_date] => 1998-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 12770
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/951/05951675.pdf
[firstpage_image] =>[orig_patent_app_number] => 179620
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/179620 | Instruction alignment unit employing dual instruction queues for high frequency instruction dispatch | Oct 26, 1998 | Issued |
Array
(
[id] => 4236577
[patent_doc_number] => 06041400
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-21
[patent_title] => 'Distributed extensible processing architecture for digital signal processing applications'
[patent_app_type] => 1
[patent_app_number] => 9/179147
[patent_app_country] => US
[patent_app_date] => 1998-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 7472
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/041/06041400.pdf
[firstpage_image] =>[orig_patent_app_number] => 179147
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/179147 | Distributed extensible processing architecture for digital signal processing applications | Oct 25, 1998 | Issued |
Array
(
[id] => 4374261
[patent_doc_number] => 06292886
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-18
[patent_title] => 'Scalar hardware for performing SIMD operations'
[patent_app_type] => 1
[patent_app_number] => 9/169865
[patent_app_country] => US
[patent_app_date] => 1998-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 5328
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/292/06292886.pdf
[firstpage_image] =>[orig_patent_app_number] => 169865
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/169865 | Scalar hardware for performing SIMD operations | Oct 11, 1998 | Issued |
Array
(
[id] => 4423825
[patent_doc_number] => 06240507
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-29
[patent_title] => 'Mechanism for multiple register renaming and method therefor'
[patent_app_type] => 1
[patent_app_number] => 9/168794
[patent_app_country] => US
[patent_app_date] => 1998-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3410
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/240/06240507.pdf
[firstpage_image] =>[orig_patent_app_number] => 168794
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/168794 | Mechanism for multiple register renaming and method therefor | Oct 7, 1998 | Issued |
| 09/168040 | METHOD AND APPARATUS FOR OPTIMIZING INSTRUCTION EXECUTION | Oct 6, 1998 | Abandoned |
Array
(
[id] => 1049648
[patent_doc_number] => 06865668
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-03-08
[patent_title] => 'Variable-length, high-speed asynchronous decoder circuit'
[patent_app_type] => utility
[patent_app_number] => 09/787168
[patent_app_country] => US
[patent_app_date] => 1998-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 33
[patent_no_of_words] => 11967
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/865/06865668.pdf
[firstpage_image] =>[orig_patent_app_number] => 09787168
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/787168 | Variable-length, high-speed asynchronous decoder circuit | Sep 29, 1998 | Issued |
Array
(
[id] => 328616
[patent_doc_number] => RE040693
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2009-03-31
[patent_title] => 'Method and apparatus for creating a wireframe and polygon virtual world'
[patent_app_type] => reissue
[patent_app_number] => 09/159509
[patent_app_country] => US
[patent_app_date] => 1998-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 1911
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/040/RE040693.pdf
[firstpage_image] =>[orig_patent_app_number] => 09159509
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/159509 | Method and apparatus for creating a wireframe and polygon virtual world | Sep 22, 1998 | Issued |
Array
(
[id] => 6988715
[patent_doc_number] => 20010037444
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-11-01
[patent_title] => 'INSTRUCTION BUFFERING MECHANISM'
[patent_app_type] => new
[patent_app_number] => 09/148638
[patent_app_country] => US
[patent_app_date] => 1998-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5342
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0037/20010037444.pdf
[firstpage_image] =>[orig_patent_app_number] => 09148638
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/148638 | INSTRUCTION BUFFERING MECHANISM | Sep 3, 1998 | Abandoned |
Array
(
[id] => 4404260
[patent_doc_number] => 06263427
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-17
[patent_title] => 'Branch prediction mechanism'
[patent_app_type] => 1
[patent_app_number] => 9/146995
[patent_app_country] => US
[patent_app_date] => 1998-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 16
[patent_no_of_words] => 7067
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/263/06263427.pdf
[firstpage_image] =>[orig_patent_app_number] => 146995
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/146995 | Branch prediction mechanism | Sep 3, 1998 | Issued |
Array
(
[id] => 6143585
[patent_doc_number] => 20020002670
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-03
[patent_title] => 'DATA PROCESSING DEVICE'
[patent_app_type] => new
[patent_app_number] => 09/146259
[patent_app_country] => US
[patent_app_date] => 1998-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 20507
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0002/20020002670.pdf
[firstpage_image] =>[orig_patent_app_number] => 09146259
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/146259 | Data processing device | Sep 2, 1998 | Issued |
Array
(
[id] => 4151975
[patent_doc_number] => 06035389
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-07
[patent_title] => 'Scheduling instructions with different latencies'
[patent_app_type] => 1
[patent_app_number] => 9/132043
[patent_app_country] => US
[patent_app_date] => 1998-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 5098
[patent_no_of_claims] => 47
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/035/06035389.pdf
[firstpage_image] =>[orig_patent_app_number] => 132043
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/132043 | Scheduling instructions with different latencies | Aug 10, 1998 | Issued |
Array
(
[id] => 1495393
[patent_doc_number] => 06418528
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-09
[patent_title] => 'Floating point unit pipeline synchronized with processor pipeline'
[patent_app_type] => B1
[patent_app_number] => 09/131881
[patent_app_country] => US
[patent_app_date] => 1998-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 36
[patent_no_of_words] => 15238
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/418/06418528.pdf
[firstpage_image] =>[orig_patent_app_number] => 09131881
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/131881 | Floating point unit pipeline synchronized with processor pipeline | Aug 9, 1998 | Issued |