Search

William M. Treat

Examiner (ID: 16215)

Most Active Art Unit
2183
Art Unit(s)
2315, 2783, 2302, 2784, 2181, 2183
Total Applications
967
Issued Applications
755
Pending Applications
33
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7080141 [patent_doc_number] => 20010042195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-15 [patent_title] => 'METHOD AND APPARATUS FOR PERFORMING PREDICATE PREDICTION' [patent_app_type] => new [patent_app_number] => 09/129141 [patent_app_country] => US [patent_app_date] => 1998-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4620 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20010042195.pdf [firstpage_image] =>[orig_patent_app_number] => 09129141 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/129141
METHOD AND APPARATUS FOR PERFORMING PREDICATE PREDICTION Aug 3, 1998 Abandoned
Array ( [id] => 4100196 [patent_doc_number] => 06055626 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Method and circuit for delayed branch control and method and circuit for conditional-flag rewriting control' [patent_app_type] => 1 [patent_app_number] => 9/120276 [patent_app_country] => US [patent_app_date] => 1998-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 7075 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055626.pdf [firstpage_image] =>[orig_patent_app_number] => 120276 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/120276
Method and circuit for delayed branch control and method and circuit for conditional-flag rewriting control Jul 21, 1998 Issued
Array ( [id] => 4427314 [patent_doc_number] => 06226737 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Apparatus and method for single precision multiplication' [patent_app_type] => 1 [patent_app_number] => 9/116189 [patent_app_country] => US [patent_app_date] => 1998-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 9723 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/226/06226737.pdf [firstpage_image] =>[orig_patent_app_number] => 116189 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/116189
Apparatus and method for single precision multiplication Jul 14, 1998 Issued
Array ( [id] => 7095090 [patent_doc_number] => 20010034828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-25 [patent_title] => 'MICROCODE SCALABLE PROCESSOR' [patent_app_type] => new [patent_app_number] => 09/109762 [patent_app_country] => US [patent_app_date] => 1998-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2287 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20010034828.pdf [firstpage_image] =>[orig_patent_app_number] => 09109762 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/109762
Microcode scalable processor Jul 1, 1998 Issued
Array ( [id] => 4373592 [patent_doc_number] => 06175863 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Storage of sitemaps at server sites for holding information regarding content' [patent_app_type] => 1 [patent_app_number] => 9/105636 [patent_app_country] => US [patent_app_date] => 1998-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5576 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175863.pdf [firstpage_image] =>[orig_patent_app_number] => 105636 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/105636
Storage of sitemaps at server sites for holding information regarding content Jun 25, 1998 Issued
Array ( [id] => 4177976 [patent_doc_number] => 06108770 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Method and apparatus for predicting memory dependence using store sets' [patent_app_type] => 1 [patent_app_number] => 9/103984 [patent_app_country] => US [patent_app_date] => 1998-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 7940 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108770.pdf [firstpage_image] =>[orig_patent_app_number] => 103984 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/103984
Method and apparatus for predicting memory dependence using store sets Jun 23, 1998 Issued
Array ( [id] => 4426441 [patent_doc_number] => 06178421 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Method of performing parallel cleanup of segments of a lock structure' [patent_app_type] => 1 [patent_app_number] => 9/092170 [patent_app_country] => US [patent_app_date] => 1998-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5716 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/178/06178421.pdf [firstpage_image] =>[orig_patent_app_number] => 092170 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/092170
Method of performing parallel cleanup of segments of a lock structure Jun 4, 1998 Issued
Array ( [id] => 4316293 [patent_doc_number] => 06185562 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Performing parallel cleanup of segments of a lock structure' [patent_app_type] => 1 [patent_app_number] => 9/092360 [patent_app_country] => US [patent_app_date] => 1998-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5892 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185562.pdf [firstpage_image] =>[orig_patent_app_number] => 092360 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/092360
Performing parallel cleanup of segments of a lock structure Jun 4, 1998 Issued
Array ( [id] => 4025370 [patent_doc_number] => 06006323 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Intelligent multiple stack management unit' [patent_app_type] => 1 [patent_app_number] => 9/082368 [patent_app_country] => US [patent_app_date] => 1998-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6412 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/006/06006323.pdf [firstpage_image] =>[orig_patent_app_number] => 082368 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/082368
Intelligent multiple stack management unit May 19, 1998 Issued
Array ( [id] => 4178088 [patent_doc_number] => 06108777 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Configurable branch prediction for a processor performing speculative execution' [patent_app_type] => 1 [patent_app_number] => 9/073499 [patent_app_country] => US [patent_app_date] => 1998-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9169 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108777.pdf [firstpage_image] =>[orig_patent_app_number] => 073499 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/073499
Configurable branch prediction for a processor performing speculative execution May 5, 1998 Issued
09/066931 INSTRUCTION BRANCHING METHOD AND A PROCESSOR Apr 27, 1998 Issued
Array ( [id] => 4374795 [patent_doc_number] => 06170050 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Length decoder for variable length data' [patent_app_type] => 1 [patent_app_number] => 9/064680 [patent_app_country] => US [patent_app_date] => 1998-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 67 [patent_no_of_words] => 12136 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/170/06170050.pdf [firstpage_image] =>[orig_patent_app_number] => 064680 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/064680
Length decoder for variable length data Apr 21, 1998 Issued
Array ( [id] => 4224241 [patent_doc_number] => 06079015 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Data processing system having selectable exception table relocation and method therefor' [patent_app_type] => 1 [patent_app_number] => 9/062952 [patent_app_country] => US [patent_app_date] => 1998-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3248 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/079/06079015.pdf [firstpage_image] =>[orig_patent_app_number] => 062952 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/062952
Data processing system having selectable exception table relocation and method therefor Apr 19, 1998 Issued
Array ( [id] => 4215648 [patent_doc_number] => 06014735 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Instruction set extension using prefixes' [patent_app_type] => 1 [patent_app_number] => 9/053391 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3835 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/014/06014735.pdf [firstpage_image] =>[orig_patent_app_number] => 053391 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/053391
Instruction set extension using prefixes Mar 30, 1998 Issued
Array ( [id] => 4310361 [patent_doc_number] => 06212618 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Apparatus and method for performing multi-dimensional computations based on intra-add operation' [patent_app_type] => 1 [patent_app_number] => 9/053388 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 3867 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212618.pdf [firstpage_image] =>[orig_patent_app_number] => 053388 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/053388
Apparatus and method for performing multi-dimensional computations based on intra-add operation Mar 30, 1998 Issued
Array ( [id] => 4270492 [patent_doc_number] => 06223276 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Pipelined processing of short data streams using data prefetching' [patent_app_type] => 1 [patent_app_number] => 9/053376 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3530 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223276.pdf [firstpage_image] =>[orig_patent_app_number] => 053376 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/053376
Pipelined processing of short data streams using data prefetching Mar 30, 1998 Issued
Array ( [id] => 4379857 [patent_doc_number] => 06192467 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Executing partial-width packed data instructions' [patent_app_type] => 1 [patent_app_number] => 9/053000 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 8833 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/192/06192467.pdf [firstpage_image] =>[orig_patent_app_number] => 053000 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/053000
Executing partial-width packed data instructions Mar 30, 1998 Issued
Array ( [id] => 4160756 [patent_doc_number] => 06061782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Mechanism for floating point to integer conversion with RGB bias multiply' [patent_app_type] => 1 [patent_app_number] => 9/048712 [patent_app_country] => US [patent_app_date] => 1998-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5151 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061782.pdf [firstpage_image] =>[orig_patent_app_number] => 048712 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/048712
Mechanism for floating point to integer conversion with RGB bias multiply Mar 25, 1998 Issued
Array ( [id] => 4215664 [patent_doc_number] => 06014736 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Apparatus and method for improved floating point exchange' [patent_app_type] => 1 [patent_app_number] => 9/048524 [patent_app_country] => US [patent_app_date] => 1998-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7268 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/014/06014736.pdf [firstpage_image] =>[orig_patent_app_number] => 048524 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/048524
Apparatus and method for improved floating point exchange Mar 25, 1998 Issued
Array ( [id] => 4076326 [patent_doc_number] => 05896526 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Programmable instruction trap system and method' [patent_app_type] => 1 [patent_app_number] => 9/025511 [patent_app_country] => US [patent_app_date] => 1998-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4233 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896526.pdf [firstpage_image] =>[orig_patent_app_number] => 025511 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/025511
Programmable instruction trap system and method Feb 17, 1998 Issued
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