William M. Treat

Array ( [id] => 3962099 [patent_doc_number] => 05974543 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Apparatus and method for performing subroutine call and return operations' [patent_app_type] => 1 [patent_app_number] => 9/024691 [patent_app_country] => US [patent_app_date] => 1998-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5595 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974543.pdf [firstpage_image] =>[orig_patent_app_number] => 024691 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3961899 [patent_doc_number] => 05974531 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Methods and systems of stack renaming for superscalar stack-based data processors' [patent_app_type] => 1 [patent_app_number] => 9/024752 [patent_app_country] => US [patent_app_date] => 1998-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8724 [patent_no_of_claims] => 95 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974531.pdf [firstpage_image] =>[orig_patent_app_number] => 024752 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4258405 [patent_doc_number] => 06092065 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Method and apparatus for discovery, clustering and classification of patterns in 1-dimensional event streams' [patent_app_type] => 1 [patent_app_number] => 9/023758 [patent_app_country] => US [patent_app_date] => 1998-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 20628 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092065.pdf [firstpage_image] =>[orig_patent_app_number] => 023758 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4215802 [patent_doc_number] => 06014743 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Apparatus and method for recording a floating point error pointer in zero cycles' [patent_app_type] => 1 [patent_app_number] => 9/019452 [patent_app_country] => US [patent_app_date] => 1998-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 9591 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/014/06014743.pdf [firstpage_image] =>[orig_patent_app_number] => 019452 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4103940 [patent_doc_number] => 06026483 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Method and apparatus for simultaneously performing arithmetic on two or more pairs of operands' [patent_app_type] => 1 [patent_app_number] => 9/014455 [patent_app_country] => US [patent_app_date] => 1998-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 9641 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026483.pdf [firstpage_image] =>[orig_patent_app_number] => 014455 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4160711 [patent_doc_number] => 06061779 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Digital signal processor having data alignment buffer for performing unaligned data accesses' [patent_app_type] => 1 [patent_app_number] => 9/008154 [patent_app_country] => US [patent_app_date] => 1998-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5290 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061779.pdf [firstpage_image] =>[orig_patent_app_number] => 008154 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4237562 [patent_doc_number] => 06112299 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Method and apparatus to select the next instruction in a superscalar or a very long instruction word computer having N-way branching' [patent_app_type] => 1 [patent_app_number] => 9/001527 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 14 [patent_no_of_words] => 9407 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/112/06112299.pdf [firstpage_image] =>[orig_patent_app_number] => 001527 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3969100 [patent_doc_number] => 05948095 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Method and apparatus for prefetching data in a computer system' [patent_app_type] => 1 [patent_app_number] => 9/001548 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3809 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/948/05948095.pdf [firstpage_image] =>[orig_patent_app_number] => 001548 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4215789 [patent_doc_number] => 06014742 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Trace branch prediction unit' [patent_app_type] => 1 [patent_app_number] => 9/002166 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6697 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/014/06014742.pdf [firstpage_image] =>[orig_patent_app_number] => 002166 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4148845 [patent_doc_number] => 06016542 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Detecting long latency pipeline stalls for thread switching' [patent_app_type] => 1 [patent_app_number] => 9/001552 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3962 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/016/06016542.pdf [firstpage_image] =>[orig_patent_app_number] => 001552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3997213 [patent_doc_number] => 05961630 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Method and apparatus for handling dynamic structural hazards and exceptions by using post-ready latency' [patent_app_type] => 1 [patent_app_number] => 9/001170 [patent_app_country] => US [patent_app_date] => 1997-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5559 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/961/05961630.pdf [firstpage_image] =>[orig_patent_app_number] => 001170 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4057620 [patent_doc_number] => 05996064 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Method and apparatus for guaranteeing minimum variable schedule distance by using post-ready latency' [patent_app_type] => 1 [patent_app_number] => 9/001251 [patent_app_country] => US [patent_app_date] => 1997-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4845 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/996/05996064.pdf [firstpage_image] =>[orig_patent_app_number] => 001251 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4026204 [patent_doc_number] => 05941982 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Efficient self-timed marking of lengthy variable length instructions' [patent_app_type] => 1 [patent_app_number] => 8/997461 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 7 [patent_no_of_words] => 7795 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/941/05941982.pdf [firstpage_image] =>[orig_patent_app_number] => 997461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4374830 [patent_doc_number] => 06170051 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Apparatus and method for program level parallelism in a VLIW processor' [patent_app_type] => 1 [patent_app_number] => 8/996526 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9654 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/170/06170051.pdf [firstpage_image] =>[orig_patent_app_number] => 996526 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4042632 [patent_doc_number] => 05931944 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Branch instruction handling in a self-timed marking system' [patent_app_type] => 1 [patent_app_number] => 8/996756 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 9 [patent_no_of_words] => 8244 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/931/05931944.pdf [firstpage_image] =>[orig_patent_app_number] => 996756 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3923987 [patent_doc_number] => 05938759 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Processor instruction control mechanism capable of decoding register instructions and immediate instructions with simple configuration' [patent_app_type] => 1 [patent_app_number] => 8/994329 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 6345 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 383 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/938/05938759.pdf [firstpage_image] =>[orig_patent_app_number] => 994329 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4269410 [patent_doc_number] => 06138232 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Microprocessor with rate of instruction operation dependent upon interrupt source for power consumption control' [patent_app_type] => 1 [patent_app_number] => 8/994834 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5588 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/138/06138232.pdf [firstpage_image] =>[orig_patent_app_number] => 994834 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3973610 [patent_doc_number] => 05978902 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Debug interface including operating system access of a serial/parallel debug port' [patent_app_type] => 1 [patent_app_number] => 8/992276 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 19768 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978902.pdf [firstpage_image] =>[orig_patent_app_number] => 992276 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4240248 [patent_doc_number] => 06012136 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Communications system with a configurable data transfer architecture' [patent_app_type] => 1 [patent_app_number] => 8/980578 [patent_app_country] => US [patent_app_date] => 1997-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 24253 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/012/06012136.pdf [firstpage_image] =>[orig_patent_app_number] => 980578 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4325773 [patent_doc_number] => 06253311 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Instruction set for bi-directional conversion and transfer of integer and floating point data' [patent_app_type] => 1 [patent_app_number] => 8/980481 [patent_app_country] => US [patent_app_date] => 1997-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4343 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/253/06253311.pdf [firstpage_image] =>[orig_patent_app_number] => 980481 [rel_patent_id] =>[rel_patent_doc_number] =>)