Search

William M. Treat

Examiner (ID: 16215)

Most Active Art Unit
2183
Art Unit(s)
2315, 2783, 2302, 2784, 2181, 2183
Total Applications
967
Issued Applications
755
Pending Applications
33
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4374326 [patent_doc_number] => 06175912 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Accumulator read port arbitration logic' [patent_app_type] => 1 [patent_app_number] => 8/970723 [patent_app_country] => US [patent_app_date] => 1997-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2703 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175912.pdf [firstpage_image] =>[orig_patent_app_number] => 970723 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/970723
Accumulator read port arbitration logic Nov 13, 1997 Issued
Array ( [id] => 4047839 [patent_doc_number] => 05857089 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-05 [patent_title] => 'Floating point stack and exchange instruction' [patent_app_type] => 1 [patent_app_number] => 8/967950 [patent_app_country] => US [patent_app_date] => 1997-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 32 [patent_no_of_words] => 14244 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/857/05857089.pdf [firstpage_image] =>[orig_patent_app_number] => 967950 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/967950
Floating point stack and exchange instruction Nov 11, 1997 Issued
Array ( [id] => 4199328 [patent_doc_number] => 06038659 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Method for using read-only memory to generate controls for microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/968120 [patent_app_country] => US [patent_app_date] => 1997-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3193 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038659.pdf [firstpage_image] =>[orig_patent_app_number] => 968120 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/968120
Method for using read-only memory to generate controls for microprocessor Nov 11, 1997 Issued
Array ( [id] => 4177451 [patent_doc_number] => 06105125 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'High speed, scalable microcode based instruction decoder for processors using split microROM access, dynamic generic microinstructions, and microcode with predecoded instruction information' [patent_app_type] => 1 [patent_app_number] => 8/968976 [patent_app_country] => US [patent_app_date] => 1997-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 10806 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/105/06105125.pdf [firstpage_image] =>[orig_patent_app_number] => 968976 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/968976
High speed, scalable microcode based instruction decoder for processors using split microROM access, dynamic generic microinstructions, and microcode with predecoded instruction information Nov 11, 1997 Issued
Array ( [id] => 4224156 [patent_doc_number] => 06079012 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Computer that selectively forces ordered execution of store and load operations between a CPU and a shared memory' [patent_app_type] => 1 [patent_app_number] => 8/968923 [patent_app_country] => US [patent_app_date] => 1997-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5011 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/079/06079012.pdf [firstpage_image] =>[orig_patent_app_number] => 968923 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/968923
Computer that selectively forces ordered execution of store and load operations between a CPU and a shared memory Nov 5, 1997 Issued
Array ( [id] => 3971355 [patent_doc_number] => 06000029 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Method and apparatus for affecting subsequent instruction processing in a data processor' [patent_app_type] => 1 [patent_app_number] => 8/963321 [patent_app_country] => US [patent_app_date] => 1997-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4306 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/000/06000029.pdf [firstpage_image] =>[orig_patent_app_number] => 963321 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/963321
Method and apparatus for affecting subsequent instruction processing in a data processor Nov 2, 1997 Issued
Array ( [id] => 4076340 [patent_doc_number] => 05896527 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Accessing data during the transition between program releases' [patent_app_type] => 1 [patent_app_number] => 8/962181 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1409 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896527.pdf [firstpage_image] =>[orig_patent_app_number] => 962181 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/962181
Accessing data during the transition between program releases Oct 30, 1997 Issued
Array ( [id] => 3916188 [patent_doc_number] => 05951679 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Microprocessor circuits, systems, and methods for issuing successive iterations of a short backward branch loop in a single cycle' [patent_app_type] => 1 [patent_app_number] => 8/962105 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 15352 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/951/05951679.pdf [firstpage_image] =>[orig_patent_app_number] => 962105 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/962105
Microprocessor circuits, systems, and methods for issuing successive iterations of a short backward branch loop in a single cycle Oct 30, 1997 Issued
Array ( [id] => 4015074 [patent_doc_number] => 05923892 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Host processor and coprocessor arrangement for processing platform-independent code' [patent_app_type] => 1 [patent_app_number] => 8/958052 [patent_app_country] => US [patent_app_date] => 1997-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 8336 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923892.pdf [firstpage_image] =>[orig_patent_app_number] => 958052 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/958052
Host processor and coprocessor arrangement for processing platform-independent code Oct 26, 1997 Issued
Array ( [id] => 4025355 [patent_doc_number] => 06006322 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Arithmetic logic unit and microprocessor capable of effectively executing processing for specific application' [patent_app_type] => 1 [patent_app_number] => 8/957783 [patent_app_country] => US [patent_app_date] => 1997-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5465 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/006/06006322.pdf [firstpage_image] =>[orig_patent_app_number] => 957783 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/957783
Arithmetic logic unit and microprocessor capable of effectively executing processing for specific application Oct 23, 1997 Issued
Array ( [id] => 4057339 [patent_doc_number] => 05909587 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Multi-chip superscalar microprocessor module' [patent_app_type] => 1 [patent_app_number] => 8/957085 [patent_app_country] => US [patent_app_date] => 1997-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6056 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909587.pdf [firstpage_image] =>[orig_patent_app_number] => 957085 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/957085
Multi-chip superscalar microprocessor module Oct 23, 1997 Issued
Array ( [id] => 4211669 [patent_doc_number] => 06044455 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Central processing unit adapted for pipeline process' [patent_app_type] => 1 [patent_app_number] => 8/956725 [patent_app_country] => US [patent_app_date] => 1997-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4022 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044455.pdf [firstpage_image] =>[orig_patent_app_number] => 956725 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/956725
Central processing unit adapted for pipeline process Oct 22, 1997 Issued
Array ( [id] => 3993014 [patent_doc_number] => 05918045 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Data processor and data processing system' [patent_app_type] => 1 [patent_app_number] => 8/953387 [patent_app_country] => US [patent_app_date] => 1997-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 7780 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/918/05918045.pdf [firstpage_image] =>[orig_patent_app_number] => 953387 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/953387
Data processor and data processing system Oct 16, 1997 Issued
08/953836 RECOVERY FROM EXCEPTION DEFERED BY SPECULATIVE INSTRUCTIONS Oct 12, 1997 Abandoned
Array ( [id] => 3935977 [patent_doc_number] => 05915117 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Computer architecture for the deferral of exceptions on speculative instructions' [patent_app_type] => 1 [patent_app_number] => 8/949295 [patent_app_country] => US [patent_app_date] => 1997-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8231 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/915/05915117.pdf [firstpage_image] =>[orig_patent_app_number] => 949295 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/949295
Computer architecture for the deferral of exceptions on speculative instructions Oct 12, 1997 Issued
Array ( [id] => 4044943 [patent_doc_number] => 05903919 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Method and apparatus for selecting a register bank' [patent_app_type] => 1 [patent_app_number] => 8/946148 [patent_app_country] => US [patent_app_date] => 1997-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3215 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903919.pdf [firstpage_image] =>[orig_patent_app_number] => 946148 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/946148
Method and apparatus for selecting a register bank Oct 6, 1997 Issued
Array ( [id] => 3997297 [patent_doc_number] => 05961636 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Checkpoint table for selective instruction flushing in a speculative execution unit' [patent_app_type] => 1 [patent_app_number] => 8/934960 [patent_app_country] => US [patent_app_date] => 1997-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4245 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/961/05961636.pdf [firstpage_image] =>[orig_patent_app_number] => 934960 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/934960
Checkpoint table for selective instruction flushing in a speculative execution unit Sep 21, 1997 Issued
Array ( [id] => 4260364 [patent_doc_number] => 06092187 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Instruction prediction based on filtering' [patent_app_type] => 1 [patent_app_number] => 8/935369 [patent_app_country] => US [patent_app_date] => 1997-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 11047 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092187.pdf [firstpage_image] =>[orig_patent_app_number] => 935369 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/935369
Instruction prediction based on filtering Sep 21, 1997 Issued
Array ( [id] => 4063806 [patent_doc_number] => 05964870 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Method and apparatus for using function context to improve branch' [patent_app_type] => 1 [patent_app_number] => 8/934964 [patent_app_country] => US [patent_app_date] => 1997-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4569 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/964/05964870.pdf [firstpage_image] =>[orig_patent_app_number] => 934964 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/934964
Method and apparatus for using function context to improve branch Sep 21, 1997 Issued
08/934280 INSTRUCTION PREDICTION BASED ON FILTERING Sep 18, 1997 Abandoned
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