Search

William M. Treat

Examiner (ID: 16215)

Most Active Art Unit
2183
Art Unit(s)
2315, 2783, 2302, 2784, 2181, 2183
Total Applications
967
Issued Applications
755
Pending Applications
33
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4063792 [patent_doc_number] => 05964869 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Instruction fetch mechanism with simultaneous prediction of control-flow instructions' [patent_app_type] => 1 [patent_app_number] => 8/878753 [patent_app_country] => US [patent_app_date] => 1997-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7958 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/964/05964869.pdf [firstpage_image] =>[orig_patent_app_number] => 878753 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/878753
Instruction fetch mechanism with simultaneous prediction of control-flow instructions Jun 18, 1997 Issued
Array ( [id] => 3778840 [patent_doc_number] => 05845103 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Computer with dynamic instruction reuse' [patent_app_type] => 1 [patent_app_number] => 8/876137 [patent_app_country] => US [patent_app_date] => 1997-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6431 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/845/05845103.pdf [firstpage_image] =>[orig_patent_app_number] => 876137 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/876137
Computer with dynamic instruction reuse Jun 12, 1997 Issued
Array ( [id] => 4068207 [patent_doc_number] => 05933629 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Apparatus and method for detecting microbranches early' [patent_app_type] => 1 [patent_app_number] => 8/873360 [patent_app_country] => US [patent_app_date] => 1997-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 15695 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933629.pdf [firstpage_image] =>[orig_patent_app_number] => 873360 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/873360
Apparatus and method for detecting microbranches early Jun 11, 1997 Issued
Array ( [id] => 4068166 [patent_doc_number] => 05933626 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Apparatus and method for tracing microprocessor instructions' [patent_app_type] => 1 [patent_app_number] => 8/874030 [patent_app_country] => US [patent_app_date] => 1997-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 15262 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933626.pdf [firstpage_image] =>[orig_patent_app_number] => 874030 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/874030
Apparatus and method for tracing microprocessor instructions Jun 11, 1997 Issued
Array ( [id] => 3818281 [patent_doc_number] => 05854912 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Flexible resource access in a microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/874031 [patent_app_country] => US [patent_app_date] => 1997-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 11435 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854912.pdf [firstpage_image] =>[orig_patent_app_number] => 874031 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/874031
Flexible resource access in a microprocessor Jun 11, 1997 Issued
Array ( [id] => 3951778 [patent_doc_number] => 05872946 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Instruction alignment unit employing dual instruction queues for high frequency instruction dispatch' [patent_app_type] => 1 [patent_app_number] => 8/873339 [patent_app_country] => US [patent_app_date] => 1997-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 12768 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/872/05872946.pdf [firstpage_image] =>[orig_patent_app_number] => 873339 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/873339
Instruction alignment unit employing dual instruction queues for high frequency instruction dispatch Jun 10, 1997 Issued
Array ( [id] => 3951327 [patent_doc_number] => 05940601 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Control circuit and method for a first-in first-out data pipeline' [patent_app_type] => 1 [patent_app_number] => 8/865900 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6105 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940601.pdf [firstpage_image] =>[orig_patent_app_number] => 865900 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/865900
Control circuit and method for a first-in first-out data pipeline May 29, 1997 Issued
Array ( [id] => 3813419 [patent_doc_number] => 05828875 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Unroll of instructions in a micro-controller' [patent_app_type] => 1 [patent_app_number] => 8/864888 [patent_app_country] => US [patent_app_date] => 1997-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10445 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828875.pdf [firstpage_image] =>[orig_patent_app_number] => 864888 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/864888
Unroll of instructions in a micro-controller May 28, 1997 Issued
Array ( [id] => 4057696 [patent_doc_number] => 05996069 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Method and circuit for delayed branch control and method and circuit for conditional-flag rewriting control' [patent_app_type] => 1 [patent_app_number] => 8/865160 [patent_app_country] => US [patent_app_date] => 1997-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 7073 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/996/05996069.pdf [firstpage_image] =>[orig_patent_app_number] => 865160 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/865160
Method and circuit for delayed branch control and method and circuit for conditional-flag rewriting control May 28, 1997 Issued
Array ( [id] => 3970098 [patent_doc_number] => 05958040 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Adaptive stream buffers' [patent_app_type] => 1 [patent_app_number] => 8/864125 [patent_app_country] => US [patent_app_date] => 1997-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6592 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/958/05958040.pdf [firstpage_image] =>[orig_patent_app_number] => 864125 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/864125
Adaptive stream buffers May 27, 1997 Issued
Array ( [id] => 3894483 [patent_doc_number] => 05826036 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Information processing apparatus' [patent_app_type] => 1 [patent_app_number] => 8/861760 [patent_app_country] => US [patent_app_date] => 1997-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5906 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/826/05826036.pdf [firstpage_image] =>[orig_patent_app_number] => 861760 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/861760
Information processing apparatus May 21, 1997 Issued
Array ( [id] => 4026247 [patent_doc_number] => 05941984 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Data processing device' [patent_app_type] => 1 [patent_app_number] => 8/857461 [patent_app_country] => US [patent_app_date] => 1997-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 40 [patent_no_of_words] => 22906 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/941/05941984.pdf [firstpage_image] =>[orig_patent_app_number] => 857461 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/857461
Data processing device May 15, 1997 Issued
Array ( [id] => 3806946 [patent_doc_number] => 05841998 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'System and method of processing instructions for a processor' [patent_app_type] => 1 [patent_app_number] => 8/853566 [patent_app_country] => US [patent_app_date] => 1997-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 8484 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841998.pdf [firstpage_image] =>[orig_patent_app_number] => 853566 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/853566
System and method of processing instructions for a processor May 8, 1997 Issued
08/854087 SYSTEM HAVING CACHE TAG MEMORY AND CACHE DATA MEMORY EXTERNAL TO AN INTEGRATED CHIP CONTAINING THE ADDDRESS GENERATING UNIT AND TAG COMPARATOR May 8, 1997 Abandoned
Array ( [id] => 4045498 [patent_doc_number] => 05943249 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Method and apparatus to perform pipelined denormalization of floating-point results' [patent_app_type] => 1 [patent_app_number] => 8/843081 [patent_app_country] => US [patent_app_date] => 1997-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5030 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943249.pdf [firstpage_image] =>[orig_patent_app_number] => 843081 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/843081
Method and apparatus to perform pipelined denormalization of floating-point results Apr 24, 1997 Issued
Array ( [id] => 4081104 [patent_doc_number] => 05867658 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Method and apparatus for implementing a stop state for a processor in a multiprocessor system' [patent_app_type] => 1 [patent_app_number] => 8/835133 [patent_app_country] => US [patent_app_date] => 1997-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3496 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867658.pdf [firstpage_image] =>[orig_patent_app_number] => 835133 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/835133
Method and apparatus for implementing a stop state for a processor in a multiprocessor system Apr 3, 1997 Issued
Array ( [id] => 3913367 [patent_doc_number] => 05835949 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Method of identifying and self-modifying code' [patent_app_type] => 1 [patent_app_number] => 8/831842 [patent_app_country] => US [patent_app_date] => 1997-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6722 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835949.pdf [firstpage_image] =>[orig_patent_app_number] => 831842 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/831842
Method of identifying and self-modifying code Apr 1, 1997 Issued
Array ( [id] => 4057693 [patent_doc_number] => 05913048 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Dispatching instructions in a processor supporting out-of-order execution' [patent_app_type] => 1 [patent_app_number] => 8/829663 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 97 [patent_no_of_words] => 12936 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/913/05913048.pdf [firstpage_image] =>[orig_patent_app_number] => 829663 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/829663
Dispatching instructions in a processor supporting out-of-order execution Mar 30, 1997 Issued
Array ( [id] => 3918691 [patent_doc_number] => 05898850 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Method and system for executing a non-native mode-sensitive instruction within a computer system' [patent_app_type] => 1 [patent_app_number] => 8/829023 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3915 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898850.pdf [firstpage_image] =>[orig_patent_app_number] => 829023 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/829023
Method and system for executing a non-native mode-sensitive instruction within a computer system Mar 30, 1997 Issued
Array ( [id] => 3984134 [patent_doc_number] => 05887161 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Issuing instructions in a processor supporting out-of-order execution' [patent_app_type] => 1 [patent_app_number] => 8/829662 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 96 [patent_no_of_words] => 13174 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/887/05887161.pdf [firstpage_image] =>[orig_patent_app_number] => 829662 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/829662
Issuing instructions in a processor supporting out-of-order execution Mar 30, 1997 Issued
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