William M. Treat

Array ( [id] => 3824876 [patent_doc_number] => 05710902 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-20 [patent_title] => 'Instruction dependency chain indentifier' [patent_app_type] => 1 [patent_app_number] => 8/524065 [patent_app_country] => US [patent_app_date] => 1995-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3869 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/710/05710902.pdf [firstpage_image] =>[orig_patent_app_number] => 524065 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3794225 [patent_doc_number] => 05809271 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Method and apparatus for changing flow of control in a processor' [patent_app_type] => 1 [patent_app_number] => 8/518563 [patent_app_country] => US [patent_app_date] => 1995-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 15921 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809271.pdf [firstpage_image] =>[orig_patent_app_number] => 518563 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3681641 [patent_doc_number] => 05600811 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-04 [patent_title] => 'Vector move instruction in a vector data processing system and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/510895 [patent_app_country] => US [patent_app_date] => 1995-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 12370 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/600/05600811.pdf [firstpage_image] =>[orig_patent_app_number] => 510895 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3672467 [patent_doc_number] => 05649103 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Method and apparatus for managing multiple server requests and collating reponses' [patent_app_type] => 1 [patent_app_number] => 8/502163 [patent_app_country] => US [patent_app_date] => 1995-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2523 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/649/05649103.pdf [firstpage_image] =>[orig_patent_app_number] => 502163 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3718752 [patent_doc_number] => 05655115 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'Processor structure and method for watchpoint of plural simultaneous unresolved branch evaluation' [patent_app_type] => 1 [patent_app_number] => 8/482075 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 61 [patent_no_of_words] => 52680 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 21 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/655/05655115.pdf [firstpage_image] =>[orig_patent_app_number] => 482075 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3670096 [patent_doc_number] => 05659721 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Processor structure and method for checkpointing instructions to maintain precise state' [patent_app_type] => 1 [patent_app_number] => 8/476419 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 64 [patent_no_of_words] => 53636 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/659/05659721.pdf [firstpage_image] =>[orig_patent_app_number] => 476419 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3682057 [patent_doc_number] => 05600838 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-04 [patent_title] => 'Object oriented dispatch and supercall process and arrangement' [patent_app_type] => 1 [patent_app_number] => 8/479785 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4327 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/600/05600838.pdf [firstpage_image] =>[orig_patent_app_number] => 479785 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3672939 [patent_doc_number] => 05649136 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Processor structure and method for maintaining and restoring precise state at any instruction boundary' [patent_app_type] => 1 [patent_app_number] => 8/483958 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 60 [patent_no_of_words] => 52593 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/649/05649136.pdf [firstpage_image] =>[orig_patent_app_number] => 483958 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3736134 [patent_doc_number] => 05673426 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-30 [patent_title] => 'Processor structure and method for tracking floating-point exceptions' [patent_app_type] => 1 [patent_app_number] => 8/484795 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 64 [patent_no_of_words] => 52804 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 415 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/673/05673426.pdf [firstpage_image] =>[orig_patent_app_number] => 484795 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3700886 [patent_doc_number] => 05644742 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Processor structure and method for a time-out checkpoint' [patent_app_type] => 1 [patent_app_number] => 8/473223 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 60 [patent_no_of_words] => 52412 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/644/05644742.pdf [firstpage_image] =>[orig_patent_app_number] => 473223 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3705745 [patent_doc_number] => 05651124 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-22 [patent_title] => 'Processor structure and method for aggressively scheduling long latency instructions including load/store instructions while maintaining precise state' [patent_app_type] => 1 [patent_app_number] => 8/478025 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 64 [patent_no_of_words] => 52833 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/651/05651124.pdf [firstpage_image] =>[orig_patent_app_number] => 478025 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3661775 [patent_doc_number] => 05606700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-25 [patent_title] => 'Computer program product and program storage device for object oriented programming platform' [patent_app_type] => 1 [patent_app_number] => 8/478798 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3282 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/606/05606700.pdf [firstpage_image] =>[orig_patent_app_number] => 478798 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3744361 [patent_doc_number] => 05636374 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-03 [patent_title] => 'Method and apparatus for performing operations based upon the addresses of microinstructions' [patent_app_type] => 1 [patent_app_number] => 8/470842 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7239 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/636/05636374.pdf [firstpage_image] =>[orig_patent_app_number] => 470842 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3761543 [patent_doc_number] => 05802314 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Method and apparatus for sending and receiving multimedia messages' [patent_app_type] => 1 [patent_app_number] => 8/461759 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 11748 [patent_no_of_claims] => 320 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802314.pdf [firstpage_image] =>[orig_patent_app_number] => 461759 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3635689 [patent_doc_number] => 05594864 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'Method and apparatus for unobtrusively monitoring processor states and characterizing bottlenecks in a pipelined processor executing grouped instructions' [patent_app_type] => 1 [patent_app_number] => 8/454406 [patent_app_country] => US [patent_app_date] => 1995-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7191 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/594/05594864.pdf [firstpage_image] =>[orig_patent_app_number] => 454406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3537134 [patent_doc_number] => 05504870 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-02 [patent_title] => 'Branch prediction device enabling simultaneous access to a content-addressed memory for retrieval and registration' [patent_app_type] => 1 [patent_app_number] => 8/448180 [patent_app_country] => US [patent_app_date] => 1995-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2566 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/504/05504870.pdf [firstpage_image] =>[orig_patent_app_number] => 448180 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3676775 [patent_doc_number] => 05598553 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-28 [patent_title] => 'Program watchpoint checking using paging with sub-page validity' [patent_app_type] => 1 [patent_app_number] => 8/444813 [patent_app_country] => US [patent_app_date] => 1995-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 8975 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/598/05598553.pdf [firstpage_image] =>[orig_patent_app_number] => 444813 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3742696 [patent_doc_number] => 05704054 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 'Counterflow pipeline processor architecture for semi-custom application specific IC\'s' [patent_app_type] => 1 [patent_app_number] => 8/438662 [patent_app_country] => US [patent_app_date] => 1995-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4030 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/704/05704054.pdf [firstpage_image] =>[orig_patent_app_number] => 438662 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3556899 [patent_doc_number] => 05555429 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-10 [patent_title] => 'Multiport RAM based multiprocessor' [patent_app_type] => 1 [patent_app_number] => 8/437447 [patent_app_country] => US [patent_app_date] => 1995-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 3997 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/555/05555429.pdf [firstpage_image] =>[orig_patent_app_number] => 437447 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3540114 [patent_doc_number] => 05542060 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-30 [patent_title] => 'Data processor including a decoding unit for decomposing a multifunctional data transfer instruction into a plurality of control codes' [patent_app_type] => 1 [patent_app_number] => 8/432334 [patent_app_country] => US [patent_app_date] => 1995-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 43 [patent_no_of_words] => 18161 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 471 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/542/05542060.pdf [firstpage_image] =>[orig_patent_app_number] => 432334 [rel_patent_id] =>[rel_patent_doc_number] =>)