Search

William M. Treat

Examiner (ID: 16215)

Most Active Art Unit
2183
Art Unit(s)
2315, 2783, 2302, 2784, 2181, 2183
Total Applications
967
Issued Applications
755
Pending Applications
33
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3507336 [patent_doc_number] => 05509130 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-16 [patent_title] => 'Method and apparatus for grouping multiple instructions, issuing grouped instructions simultaneously, and executing grouped instructions in a pipelined processor' [patent_app_type] => 1 [patent_app_number] => 8/355804 [patent_app_country] => US [patent_app_date] => 1994-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10328 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/509/05509130.pdf [firstpage_image] =>[orig_patent_app_number] => 355804 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/355804
Method and apparatus for grouping multiple instructions, issuing grouped instructions simultaneously, and executing grouped instructions in a pipelined processor Dec 13, 1994 Issued
Array ( [id] => 3616393 [patent_doc_number] => 05579493 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-26 [patent_title] => 'System with loop buffer and repeat control circuit having stack for storing control information' [patent_app_type] => 1 [patent_app_number] => 8/354166 [patent_app_country] => US [patent_app_date] => 1994-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7908 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/579/05579493.pdf [firstpage_image] =>[orig_patent_app_number] => 354166 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/354166
System with loop buffer and repeat control circuit having stack for storing control information Dec 7, 1994 Issued
Array ( [id] => 3432270 [patent_doc_number] => 05479622 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-26 [patent_title] => 'Single cycle dispatch delay in a multiple instruction dispatch mechanism of a data processing system' [patent_app_type] => 1 [patent_app_number] => 8/339315 [patent_app_country] => US [patent_app_date] => 1994-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 3257 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/479/05479622.pdf [firstpage_image] =>[orig_patent_app_number] => 339315 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/339315
Single cycle dispatch delay in a multiple instruction dispatch mechanism of a data processing system Nov 13, 1994 Issued
08/332508 SYSTEM AND METHOD FOR PRESERVING INSTRUCTION STATE-ATOMICITY FOR TRANSLATED PROGRAM CODE Oct 30, 1994 Abandoned
Array ( [id] => 3667373 [patent_doc_number] => 05623629 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Apparatus for maintaining coherency of cache memory data' [patent_app_type] => 1 [patent_app_number] => 8/323501 [patent_app_country] => US [patent_app_date] => 1994-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5420 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/623/05623629.pdf [firstpage_image] =>[orig_patent_app_number] => 323501 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/323501
Apparatus for maintaining coherency of cache memory data Oct 13, 1994 Issued
Array ( [id] => 3602455 [patent_doc_number] => 05488692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-30 [patent_title] => 'System and method for representing and manipulating three-dimensional objects on massively parallel architectures' [patent_app_type] => 1 [patent_app_number] => 8/289181 [patent_app_country] => US [patent_app_date] => 1994-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4795 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/488/05488692.pdf [firstpage_image] =>[orig_patent_app_number] => 289181 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/289181
System and method for representing and manipulating three-dimensional objects on massively parallel architectures Aug 10, 1994 Issued
Array ( [id] => 3600868 [patent_doc_number] => 05517600 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-14 [patent_title] => 'Neuro-chip and neurocomputer having the chip' [patent_app_type] => 1 [patent_app_number] => 8/285767 [patent_app_country] => US [patent_app_date] => 1994-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 12164 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/517/05517600.pdf [firstpage_image] =>[orig_patent_app_number] => 285767 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/285767
Neuro-chip and neurocomputer having the chip Aug 2, 1994 Issued
Array ( [id] => 3133333 [patent_doc_number] => 05450584 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-12 [patent_title] => 'Apparatus and method for automatic transfer of data base information in response to load distribution among interconnected terminal stations' [patent_app_type] => 1 [patent_app_number] => 8/270785 [patent_app_country] => US [patent_app_date] => 1994-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3458 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/450/05450584.pdf [firstpage_image] =>[orig_patent_app_number] => 270785 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/270785
Apparatus and method for automatic transfer of data base information in response to load distribution among interconnected terminal stations Jul 4, 1994 Issued
Array ( [id] => 3592391 [patent_doc_number] => 05499348 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-12 [patent_title] => 'Digital processor capable of concurrently executing external memory access and internal instructions' [patent_app_type] => 1 [patent_app_number] => 8/266104 [patent_app_country] => US [patent_app_date] => 1994-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 3685 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/499/05499348.pdf [firstpage_image] =>[orig_patent_app_number] => 266104 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/266104
Digital processor capable of concurrently executing external memory access and internal instructions Jun 26, 1994 Issued
08/252411 METHOD AND APPARATUS FOR SIMULTANEOUSLY EXECUTING INSTRUCTIONS IN A PIPELINED MICROPROCESSOR May 31, 1994 Abandoned
Array ( [id] => 3700710 [patent_doc_number] => 05696955 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Floating point stack and exchange instruction' [patent_app_type] => 1 [patent_app_number] => 8/252303 [patent_app_country] => US [patent_app_date] => 1994-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 32 [patent_no_of_words] => 14243 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696955.pdf [firstpage_image] =>[orig_patent_app_number] => 252303 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/252303
Floating point stack and exchange instruction May 31, 1994 Issued
Array ( [id] => 3735117 [patent_doc_number] => 05682552 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Data communication adapter and data communication terminal apparatus for performing data transmission and reception between terminals' [patent_app_type] => 1 [patent_app_number] => 8/248529 [patent_app_country] => US [patent_app_date] => 1994-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 10577 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/682/05682552.pdf [firstpage_image] =>[orig_patent_app_number] => 248529 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/248529
Data communication adapter and data communication terminal apparatus for performing data transmission and reception between terminals May 23, 1994 Issued
08/239170 SINGLE CYCLE DISPATCH DELAY IN A MULTIPLE INSTRUCTION DISPATCH MECHANISM OF A DATA PROCESSING SYSTEM May 5, 1994 Abandoned
08/234207 A COMPUTER THAT SELECTIVELY FORCES ORDERED EXECUTION OF STORE AND LOAD OPERATIONS BETWEEN A CPU AND A SHARED MEMORY Apr 27, 1994 Abandoned
Array ( [id] => 3675758 [patent_doc_number] => 05625809 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-29 [patent_title] => 'Method for constructing a data structure which allows data to be shared between programs' [patent_app_type] => 1 [patent_app_number] => 8/231861 [patent_app_country] => US [patent_app_date] => 1994-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 83 [patent_figures_cnt] => 87 [patent_no_of_words] => 10789 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/625/05625809.pdf [firstpage_image] =>[orig_patent_app_number] => 231861 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/231861
Method for constructing a data structure which allows data to be shared between programs Apr 21, 1994 Issued
Array ( [id] => 3133703 [patent_doc_number] => 05381533 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-10 [patent_title] => 'Dynamic flow instruction cache memory organized around trace segments independent of virtual address line' [patent_app_type] => 1 [patent_app_number] => 8/220391 [patent_app_country] => US [patent_app_date] => 1994-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 7084 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/381/05381533.pdf [firstpage_image] =>[orig_patent_app_number] => 220391 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/220391
Dynamic flow instruction cache memory organized around trace segments independent of virtual address line Mar 29, 1994 Issued
Array ( [id] => 3518747 [patent_doc_number] => 05515526 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-07 [patent_title] => 'Apparatus for detecting redundant circuit included in logic circuit and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/214996 [patent_app_country] => US [patent_app_date] => 1994-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2806 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/515/05515526.pdf [firstpage_image] =>[orig_patent_app_number] => 214996 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/214996
Apparatus for detecting redundant circuit included in logic circuit and method therefor Mar 20, 1994 Issued
Array ( [id] => 3627063 [patent_doc_number] => 05535407 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'Data processing system for locally updating customer data distributed by a host computer to a remote facility and for returning the updated customer data to the host computer' [patent_app_type] => 1 [patent_app_number] => 8/201712 [patent_app_country] => US [patent_app_date] => 1994-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4843 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 510 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/535/05535407.pdf [firstpage_image] =>[orig_patent_app_number] => 201712 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/201712
Data processing system for locally updating customer data distributed by a host computer to a remote facility and for returning the updated customer data to the host computer Feb 24, 1994 Issued
Array ( [id] => 3540075 [patent_doc_number] => 05542057 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-30 [patent_title] => 'Method for controlling vector data execution' [patent_app_type] => 1 [patent_app_number] => 8/199973 [patent_app_country] => US [patent_app_date] => 1994-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2972 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/542/05542057.pdf [firstpage_image] =>[orig_patent_app_number] => 199973 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/199973
Method for controlling vector data execution Feb 21, 1994 Issued
Array ( [id] => 3505446 [patent_doc_number] => 05537559 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-16 [patent_title] => 'Exception handling circuit and method' [patent_app_type] => 1 [patent_app_number] => 8/193241 [patent_app_country] => US [patent_app_date] => 1994-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6565 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/537/05537559.pdf [firstpage_image] =>[orig_patent_app_number] => 193241 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/193241
Exception handling circuit and method Feb 7, 1994 Issued
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