| Application number | Title of the application | Filing Date | Status |
|---|
Array
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Array
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[patent_doc_number] => 05579493
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-26
[patent_title] => 'System with loop buffer and repeat control circuit having stack for storing control information'
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[patent_app_number] => 8/354166
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/354166 | System with loop buffer and repeat control circuit having stack for storing control information | Dec 7, 1994 | Issued |
Array
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[id] => 3432270
[patent_doc_number] => 05479622
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-26
[patent_title] => 'Single cycle dispatch delay in a multiple instruction dispatch mechanism of a data processing system'
[patent_app_type] => 1
[patent_app_number] => 8/339315
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[patent_app_date] => 1994-11-14
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| 08/332508 | SYSTEM AND METHOD FOR PRESERVING INSTRUCTION STATE-ATOMICITY FOR TRANSLATED PROGRAM CODE | Oct 30, 1994 | Abandoned |
Array
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[id] => 3667373
[patent_doc_number] => 05623629
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-22
[patent_title] => 'Apparatus for maintaining coherency of cache memory data'
[patent_app_type] => 1
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Array
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[patent_issue_date] => 1996-01-30
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Array
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Array
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[patent_issue_date] => 1995-09-12
[patent_title] => 'Apparatus and method for automatic transfer of data base information in response to load distribution among interconnected terminal stations'
[patent_app_type] => 1
[patent_app_number] => 8/270785
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[firstpage_image] =>[orig_patent_app_number] => 270785
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/270785 | Apparatus and method for automatic transfer of data base information in response to load distribution among interconnected terminal stations | Jul 4, 1994 | Issued |
Array
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[id] => 3592391
[patent_doc_number] => 05499348
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-03-12
[patent_title] => 'Digital processor capable of concurrently executing external memory access and internal instructions'
[patent_app_type] => 1
[patent_app_number] => 8/266104
[patent_app_country] => US
[patent_app_date] => 1994-06-27
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[pdf_file] => patents/05/499/05499348.pdf
[firstpage_image] =>[orig_patent_app_number] => 266104
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/266104 | Digital processor capable of concurrently executing external memory access and internal instructions | Jun 26, 1994 | Issued |
| 08/252411 | METHOD AND APPARATUS FOR SIMULTANEOUSLY EXECUTING INSTRUCTIONS IN A PIPELINED MICROPROCESSOR | May 31, 1994 | Abandoned |
Array
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[id] => 3700710
[patent_doc_number] => 05696955
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[patent_kind] => NA
[patent_issue_date] => 1997-12-09
[patent_title] => 'Floating point stack and exchange instruction'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/252303 | Floating point stack and exchange instruction | May 31, 1994 | Issued |
Array
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[id] => 3735117
[patent_doc_number] => 05682552
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-28
[patent_title] => 'Data communication adapter and data communication terminal apparatus for performing data transmission and reception between terminals'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/248529 | Data communication adapter and data communication terminal apparatus for performing data transmission and reception between terminals | May 23, 1994 | Issued |
| 08/239170 | SINGLE CYCLE DISPATCH DELAY IN A MULTIPLE INSTRUCTION DISPATCH MECHANISM OF A DATA PROCESSING SYSTEM | May 5, 1994 | Abandoned |
| 08/234207 | A COMPUTER THAT SELECTIVELY FORCES ORDERED EXECUTION OF STORE AND LOAD OPERATIONS BETWEEN A CPU AND A SHARED MEMORY | Apr 27, 1994 | Abandoned |
Array
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Array
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Array
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Array
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Array
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