Search

William M. Treat

Examiner (ID: 16215)

Most Active Art Unit
2183
Art Unit(s)
2315, 2783, 2302, 2784, 2181, 2183
Total Applications
967
Issued Applications
755
Pending Applications
33
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5114957 [patent_doc_number] => 20070198873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Method of Operation of a Microprocessor' [patent_app_type] => utility [patent_app_number] => 11/565874 [patent_app_country] => US [patent_app_date] => 2006-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4139 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20070198873.pdf [firstpage_image] =>[orig_patent_app_number] => 11565874 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/565874
Method of Operation of a Microprocessor Nov 30, 2006 Abandoned
Array ( [id] => 846209 [patent_doc_number] => 07389408 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-06-17 [patent_title] => 'Microarchitecture for compact storage of embedded constants' [patent_app_type] => utility [patent_app_number] => 11/566206 [patent_app_country] => US [patent_app_date] => 2006-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 14606 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/389/07389408.pdf [firstpage_image] =>[orig_patent_app_number] => 11566206 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/566206
Microarchitecture for compact storage of embedded constants Nov 30, 2006 Issued
Array ( [id] => 321723 [patent_doc_number] => 07523446 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-21 [patent_title] => 'User-space return probes' [patent_app_type] => utility [patent_app_number] => 11/565346 [patent_app_country] => US [patent_app_date] => 2006-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4498 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/523/07523446.pdf [firstpage_image] =>[orig_patent_app_number] => 11565346 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/565346
User-space return probes Nov 29, 2006 Issued
Array ( [id] => 127997 [patent_doc_number] => 07707388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Computer memory architecture for hybrid serial and parallel computing systems' [patent_app_type] => utility [patent_app_number] => 11/606860 [patent_app_country] => US [patent_app_date] => 2006-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7443 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/707/07707388.pdf [firstpage_image] =>[orig_patent_app_number] => 11606860 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/606860
Computer memory architecture for hybrid serial and parallel computing systems Nov 28, 2006 Issued
Array ( [id] => 599153 [patent_doc_number] => 07444501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Methods and apparatus for recognizing a subroutine call' [patent_app_type] => utility [patent_app_number] => 11/563943 [patent_app_country] => US [patent_app_date] => 2006-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4860 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/444/07444501.pdf [firstpage_image] =>[orig_patent_app_number] => 11563943 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/563943
Methods and apparatus for recognizing a subroutine call Nov 27, 2006 Issued
Array ( [id] => 156217 [patent_doc_number] => 07681019 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-16 [patent_title] => 'Executing functions determined via a collection of operations from translated instructions' [patent_app_type] => utility [patent_app_number] => 11/561287 [patent_app_country] => US [patent_app_date] => 2006-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 21923 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/681/07681019.pdf [firstpage_image] =>[orig_patent_app_number] => 11561287 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/561287
Executing functions determined via a collection of operations from translated instructions Nov 16, 2006 Issued
Array ( [id] => 5042162 [patent_doc_number] => 20070094444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'System with high power and low power processors and thread transfer' [patent_app_type] => utility [patent_app_number] => 11/599544 [patent_app_country] => US [patent_app_date] => 2006-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 20898 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20070094444.pdf [firstpage_image] =>[orig_patent_app_number] => 11599544 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/599544
System with high power and low power processors and thread transfer Nov 13, 2006 Abandoned
Array ( [id] => 4905628 [patent_doc_number] => 20080115042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-15 [patent_title] => 'Critical section detection and prediction mechanism for hardware lock elision' [patent_app_type] => utility [patent_app_number] => 11/599009 [patent_app_country] => US [patent_app_date] => 2006-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9292 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20080115042.pdf [firstpage_image] =>[orig_patent_app_number] => 11599009 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/599009
Critical section detection and prediction mechanism for hardware lock elision Nov 12, 2006 Issued
Array ( [id] => 4498848 [patent_doc_number] => 07886135 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-02-08 [patent_title] => 'Pipeline replay support for unaligned memory operations' [patent_app_type] => utility [patent_app_number] => 11/594672 [patent_app_country] => US [patent_app_date] => 2006-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 8974 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/886/07886135.pdf [firstpage_image] =>[orig_patent_app_number] => 11594672 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/594672
Pipeline replay support for unaligned memory operations Nov 6, 2006 Issued
Array ( [id] => 7595784 [patent_doc_number] => 07620798 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-11-17 [patent_title] => 'Latency tolerant pipeline synchronization' [patent_app_type] => utility [patent_app_number] => 11/554511 [patent_app_country] => US [patent_app_date] => 2006-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4840 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/620/07620798.pdf [firstpage_image] =>[orig_patent_app_number] => 11554511 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/554511
Latency tolerant pipeline synchronization Oct 29, 2006 Issued
Array ( [id] => 5000897 [patent_doc_number] => 20070043531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Method and apparatus for precisely identifying effective addresses associated with hardware events' [patent_app_type] => utility [patent_app_number] => 11/589492 [patent_app_country] => US [patent_app_date] => 2006-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 41748 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20070043531.pdf [firstpage_image] =>[orig_patent_app_number] => 11589492 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/589492
Method and apparatus for precisely identifying effective addresses associated with hardware events Oct 29, 2006 Issued
Array ( [id] => 4917802 [patent_doc_number] => 20080098403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'DATA FLOW EXECUTION OF METHODS IN SEQUENTIAL PROGRAMS' [patent_app_type] => utility [patent_app_number] => 11/550687 [patent_app_country] => US [patent_app_date] => 2006-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4725 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20080098403.pdf [firstpage_image] =>[orig_patent_app_number] => 11550687 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/550687
Data flow execution of methods in sequential programs Oct 17, 2006 Issued
Array ( [id] => 237792 [patent_doc_number] => 07596781 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-29 [patent_title] => 'Register-based instruction optimization for facilitating efficient emulation of an instruction stream' [patent_app_type] => utility [patent_app_number] => 11/549718 [patent_app_country] => US [patent_app_date] => 2006-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5169 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/596/07596781.pdf [firstpage_image] =>[orig_patent_app_number] => 11549718 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/549718
Register-based instruction optimization for facilitating efficient emulation of an instruction stream Oct 15, 2006 Issued
Array ( [id] => 4747319 [patent_doc_number] => 20080091921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'DATA PREFETCHING IN A MICROPROCESSING ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 11/548711 [patent_app_country] => US [patent_app_date] => 2006-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4967 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20080091921.pdf [firstpage_image] =>[orig_patent_app_number] => 11548711 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/548711
DATA PREFETCHING IN A MICROPROCESSING ENVIRONMENT Oct 11, 2006 Abandoned
Array ( [id] => 118168 [patent_doc_number] => 07716454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-11 [patent_title] => 'Method and apparatus for matrix decomposition in programmable logic devices' [patent_app_type] => utility [patent_app_number] => 11/546540 [patent_app_country] => US [patent_app_date] => 2006-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 8274 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/716/07716454.pdf [firstpage_image] =>[orig_patent_app_number] => 11546540 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/546540
Method and apparatus for matrix decomposition in programmable logic devices Oct 9, 2006 Issued
Array ( [id] => 4693851 [patent_doc_number] => 20080086622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'Replay reduction for power saving' [patent_app_type] => utility [patent_app_number] => 11/546223 [patent_app_country] => US [patent_app_date] => 2006-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6599 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20080086622.pdf [firstpage_image] =>[orig_patent_app_number] => 11546223 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/546223
Replay reduction for power saving Oct 9, 2006 Issued
Array ( [id] => 5195310 [patent_doc_number] => 20070083795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'Securised microprocessor with jump verification' [patent_app_type] => utility [patent_app_number] => 11/544596 [patent_app_country] => US [patent_app_date] => 2006-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2129 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20070083795.pdf [firstpage_image] =>[orig_patent_app_number] => 11544596 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/544596
Securised microprocessor with jump verification Oct 9, 2006 Abandoned
Array ( [id] => 5260710 [patent_doc_number] => 20070214343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'ACROSS-THREAD OUT-OF-ORDER INSTRUCTION DISPATCH IN A MULTITHREADED MICROPROCESSOR' [patent_app_type] => utility [patent_app_number] => 11/548272 [patent_app_country] => US [patent_app_date] => 2006-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11968 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20070214343.pdf [firstpage_image] =>[orig_patent_app_number] => 11548272 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/548272
Across-thread out-of-order instruction dispatch in a multithreaded microprocessor Oct 9, 2006 Issued
Array ( [id] => 4527636 [patent_doc_number] => 07934081 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-26 [patent_title] => 'Apparatus and method for using branch prediction heuristics for determination of trace formation readiness' [patent_app_type] => utility [patent_app_number] => 11/538831 [patent_app_country] => US [patent_app_date] => 2006-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2487 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 391 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/934/07934081.pdf [firstpage_image] =>[orig_patent_app_number] => 11538831 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/538831
Apparatus and method for using branch prediction heuristics for determination of trace formation readiness Oct 4, 2006 Issued
Array ( [id] => 371983 [patent_doc_number] => 07478226 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-01-13 [patent_title] => 'Processing bypass directory tracking system and method' [patent_app_type] => utility [patent_app_number] => 11/540789 [patent_app_country] => US [patent_app_date] => 2006-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3254 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/478/07478226.pdf [firstpage_image] =>[orig_patent_app_number] => 11540789 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/540789
Processing bypass directory tracking system and method Sep 28, 2006 Issued
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