Search

William M. Treat

Examiner (ID: 16215)

Most Active Art Unit
2183
Art Unit(s)
2315, 2783, 2302, 2784, 2181, 2183
Total Applications
967
Issued Applications
755
Pending Applications
33
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 137130 [patent_doc_number] => 07698449 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-04-13 [patent_title] => 'Method and apparatus for configuring a processor embedded in an integrated circuit for use as a logic element' [patent_app_type] => utility [patent_app_number] => 11/064148 [patent_app_country] => US [patent_app_date] => 2005-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4370 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/698/07698449.pdf [firstpage_image] =>[orig_patent_app_number] => 11064148 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/064148
Method and apparatus for configuring a processor embedded in an integrated circuit for use as a logic element Feb 22, 2005 Issued
Array ( [id] => 5896454 [patent_doc_number] => 20060004993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Processor and pipeline reconfiguration control method' [patent_app_type] => utility [patent_app_number] => 11/063860 [patent_app_country] => US [patent_app_date] => 2005-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3011 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20060004993.pdf [firstpage_image] =>[orig_patent_app_number] => 11063860 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/063860
Processor and pipeline reconfiguration control method Feb 22, 2005 Issued
Array ( [id] => 5621172 [patent_doc_number] => 20060190707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'System and method of correcting a branch misprediction' [patent_app_type] => utility [patent_app_number] => 11/061981 [patent_app_country] => US [patent_app_date] => 2005-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3055 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190707.pdf [firstpage_image] =>[orig_patent_app_number] => 11061981 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/061981
System and method of correcting a branch misprediction Feb 17, 2005 Issued
Array ( [id] => 5621176 [patent_doc_number] => 20060190711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Method and apparatus for managing a return stack' [patent_app_type] => utility [patent_app_number] => 11/061975 [patent_app_country] => US [patent_app_date] => 2005-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3786 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190711.pdf [firstpage_image] =>[orig_patent_app_number] => 11061975 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/061975
Method and apparatus for managing a return stack Feb 17, 2005 Issued
Array ( [id] => 5679412 [patent_doc_number] => 20060184768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-17 [patent_title] => 'Method and apparatus for dynamic modification of microprocessor instruction group at dispatch' [patent_app_type] => utility [patent_app_number] => 11/055831 [patent_app_country] => US [patent_app_date] => 2005-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6093 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20060184768.pdf [firstpage_image] =>[orig_patent_app_number] => 11055831 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/055831
Method and apparatus for dynamic modification of microprocessor instruction group at dispatch Feb 10, 2005 Issued
Array ( [id] => 839887 [patent_doc_number] => 07395414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-01 [patent_title] => 'Dynamic recalculation of resource vector at issue queue for steering of dependent instructions' [patent_app_type] => utility [patent_app_number] => 11/056691 [patent_app_country] => US [patent_app_date] => 2005-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5597 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/395/07395414.pdf [firstpage_image] =>[orig_patent_app_number] => 11056691 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/056691
Dynamic recalculation of resource vector at issue queue for steering of dependent instructions Feb 10, 2005 Issued
Array ( [id] => 5673935 [patent_doc_number] => 20060179290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-10 [patent_title] => 'System and method for creating precise exceptions' [patent_app_type] => utility [patent_app_number] => 11/055193 [patent_app_country] => US [patent_app_date] => 2005-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2660 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20060179290.pdf [firstpage_image] =>[orig_patent_app_number] => 11055193 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/055193
System and method for creating precise exceptions Feb 9, 2005 Issued
Array ( [id] => 5673933 [patent_doc_number] => 20060179288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-10 [patent_title] => 'Conditional instruction execution via emissary instruction for condition evaluation' [patent_app_type] => utility [patent_app_number] => 11/055919 [patent_app_country] => US [patent_app_date] => 2005-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2483 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20060179288.pdf [firstpage_image] =>[orig_patent_app_number] => 11055919 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/055919
Conditional instruction execution via emissary instruction for condition evaluation Feb 9, 2005 Issued
Array ( [id] => 539595 [patent_doc_number] => 07188233 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-06 [patent_title] => 'System and method for performing floating point store folding' [patent_app_type] => utility [patent_app_number] => 11/054686 [patent_app_country] => US [patent_app_date] => 2005-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7057 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/188/07188233.pdf [firstpage_image] =>[orig_patent_app_number] => 11054686 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/054686
System and method for performing floating point store folding Feb 8, 2005 Issued
Array ( [id] => 5673922 [patent_doc_number] => 20060179277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-10 [patent_title] => 'System and method for instruction line buffer holding a branch target buffer' [patent_app_type] => utility [patent_app_number] => 11/052502 [patent_app_country] => US [patent_app_date] => 2005-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 57 [patent_no_of_words] => 16592 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20060179277.pdf [firstpage_image] =>[orig_patent_app_number] => 11052502 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/052502
System and method for instruction line buffer holding a branch target buffer Feb 3, 2005 Abandoned
Array ( [id] => 5668741 [patent_doc_number] => 20060174091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-03 [patent_title] => 'Instruction grouping history on fetch-side dispatch group formation' [patent_app_type] => utility [patent_app_number] => 11/050344 [patent_app_country] => US [patent_app_date] => 2005-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6195 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20060174091.pdf [firstpage_image] =>[orig_patent_app_number] => 11050344 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/050344
Instruction grouping history on fetch-side dispatch group formation Feb 2, 2005 Issued
Array ( [id] => 107740 [patent_doc_number] => 07725698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'Operation apparatus having sequencer controlling states of plurality of operation units and operation apparatus control method therefor' [patent_app_type] => utility [patent_app_number] => 11/042333 [patent_app_country] => US [patent_app_date] => 2005-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 55 [patent_no_of_words] => 12643 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/725/07725698.pdf [firstpage_image] =>[orig_patent_app_number] => 11042333 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/042333
Operation apparatus having sequencer controlling states of plurality of operation units and operation apparatus control method therefor Jan 25, 2005 Issued
Array ( [id] => 890561 [patent_doc_number] => 07353370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-01 [patent_title] => 'Method and apparatus for processing an event occurrence within a multithreaded processor' [patent_app_type] => utility [patent_app_number] => 11/040773 [patent_app_country] => US [patent_app_date] => 2005-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 16472 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/353/07353370.pdf [firstpage_image] =>[orig_patent_app_number] => 11040773 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/040773
Method and apparatus for processing an event occurrence within a multithreaded processor Jan 19, 2005 Issued
Array ( [id] => 5221413 [patent_doc_number] => 20070162725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'Method and related device for use in decoding executable code' [patent_app_type] => utility [patent_app_number] => 10/585801 [patent_app_country] => US [patent_app_date] => 2005-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2010 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20070162725.pdf [firstpage_image] =>[orig_patent_app_number] => 10585801 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/585801
Method and related device for use in decoding executable code Jan 10, 2005 Issued
Array ( [id] => 7166832 [patent_doc_number] => 20050086452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Enhanced boolean processor with parallel input' [patent_app_type] => utility [patent_app_number] => 11/005666 [patent_app_country] => US [patent_app_date] => 2004-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 34261 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20050086452.pdf [firstpage_image] =>[orig_patent_app_number] => 11005666 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/005666
Enhanced boolean processor with parallel input Dec 6, 2004 Abandoned
Array ( [id] => 619743 [patent_doc_number] => 07146491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-05 [patent_title] => 'Apparatus and method for generating constant values' [patent_app_type] => utility [patent_app_number] => 10/972769 [patent_app_country] => US [patent_app_date] => 2004-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5093 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/146/07146491.pdf [firstpage_image] =>[orig_patent_app_number] => 10972769 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/972769
Apparatus and method for generating constant values Oct 25, 2004 Issued
Array ( [id] => 6941076 [patent_doc_number] => 20050114639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Hardened extensible firmware framework to support system management mode operations using 64-bit extended memory mode processors' [patent_app_type] => utility [patent_app_number] => 10/971824 [patent_app_country] => US [patent_app_date] => 2004-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8898 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20050114639.pdf [firstpage_image] =>[orig_patent_app_number] => 10971824 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/971824
Hardened extensible firmware framework to support system management mode operations using 64-bit extended memory mode processors Oct 20, 2004 Abandoned
Array ( [id] => 5867125 [patent_doc_number] => 20060101256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Looping instructions for a single instruction, multiple data execution engine' [patent_app_type] => utility [patent_app_number] => 10/969731 [patent_app_country] => US [patent_app_date] => 2004-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 5148 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20060101256.pdf [firstpage_image] =>[orig_patent_app_number] => 10969731 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/969731
Looping instructions for a single instruction, multiple data execution engine Oct 19, 2004 Abandoned
Array ( [id] => 8207563 [patent_doc_number] => 08190669 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-05-29 [patent_title] => 'Multipurpose arithmetic functional unit' [patent_app_type] => utility [patent_app_number] => 10/970253 [patent_app_country] => US [patent_app_date] => 2004-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 13901 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 481 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/190/08190669.pdf [firstpage_image] =>[orig_patent_app_number] => 10970253 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/970253
Multipurpose arithmetic functional unit Oct 19, 2004 Issued
Array ( [id] => 6992437 [patent_doc_number] => 20050091474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-28 [patent_title] => 'Fuse configurable alternate behavior of a central processing unit' [patent_app_type] => utility [patent_app_number] => 10/969512 [patent_app_country] => US [patent_app_date] => 2004-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1955 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20050091474.pdf [firstpage_image] =>[orig_patent_app_number] => 10969512 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/969512
Fuse configurable alternate behavior of a central processing unit Oct 19, 2004 Abandoned
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