William O Sandals

Array ( [id] => 3456888 [patent_doc_number] => 05388247 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-07 [patent_title] => 'History buffer control to reduce unnecessary allocations in a memory stream buffer' [patent_app_type] => 1 [patent_app_number] => 8/197376 [patent_app_country] => US [patent_app_date] => 1994-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 12653 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/388/05388247.pdf [firstpage_image] =>[orig_patent_app_number] => 197376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3456857 [patent_doc_number] => 05388245 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-07 [patent_title] => 'Memory arbitration method and apparatus for multiple-cycle memory coprocessors employing a data cache unit and stack RAM' [patent_app_type] => 1 [patent_app_number] => 8/069917 [patent_app_country] => US [patent_app_date] => 1993-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5767 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/388/05388245.pdf [firstpage_image] =>[orig_patent_app_number] => 069917 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3128825 [patent_doc_number] => 05410671 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-25 [patent_title] => 'Data compression/decompression processor' [patent_app_type] => 1 [patent_app_number] => 8/066317 [patent_app_country] => US [patent_app_date] => 1993-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 15294 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/410/05410671.pdf [firstpage_image] =>[orig_patent_app_number] => 066317 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3079505 [patent_doc_number] => 05353427 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-04 [patent_title] => 'Semiconductor memory device for simple cache system with selective coupling of bit line pairs' [patent_app_type] => 1 [patent_app_number] => 8/063487 [patent_app_country] => US [patent_app_date] => 1993-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9192 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/353/05353427.pdf [firstpage_image] =>[orig_patent_app_number] => 063487 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3473449 [patent_doc_number] => 05392418 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'Programmable read only memory with output indicating programming state' [patent_app_type] => 1 [patent_app_number] => 7/837189 [patent_app_country] => US [patent_app_date] => 1992-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1163 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/392/05392418.pdf [firstpage_image] =>[orig_patent_app_number] => 837189 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3069317 [patent_doc_number] => 05357623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-18 [patent_title] => 'Dynamic cache partitioning by modified steepest descent' [patent_app_type] => 1 [patent_app_number] => 7/786490 [patent_app_country] => US [patent_app_date] => 1991-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4193 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/357/05357623.pdf [firstpage_image] =>[orig_patent_app_number] => 786490 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3465233 [patent_doc_number] => 05379396 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-03 [patent_title] => 'Write ordering for microprocessor depending on cache hit and write buffer content' [patent_app_type] => 1 [patent_app_number] => 7/777765 [patent_app_country] => US [patent_app_date] => 1991-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 8457 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/379/05379396.pdf [firstpage_image] =>[orig_patent_app_number] => 777765 [rel_patent_id] =>[rel_patent_doc_number] =>)