William P Neuder

Array ( [id] => 4350745 [patent_doc_number] => 06334169 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'System and method for improved bitwrite capability in a field programmable memory array' [patent_app_type] => 1 [patent_app_number] => 9/163691 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2941 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 395 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/334/06334169.pdf [firstpage_image] =>[orig_patent_app_number] => 163691 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6866387 [patent_doc_number] => 20030191913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-09 [patent_title] => 'TRACKING MEMORY PAGE STATE' [patent_app_type] => new [patent_app_number] => 09/164088 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4128 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20030191913.pdf [firstpage_image] =>[orig_patent_app_number] => 09164088 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4324554 [patent_doc_number] => 06327643 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'System and method for cache line replacement' [patent_app_type] => 1 [patent_app_number] => 9/163921 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 3704 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327643.pdf [firstpage_image] =>[orig_patent_app_number] => 163921 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4402332 [patent_doc_number] => 06279090 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device' [patent_app_type] => 1 [patent_app_number] => 9/146716 [patent_app_country] => US [patent_app_date] => 1998-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 33465 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279090.pdf [firstpage_image] =>[orig_patent_app_number] => 146716 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1497836 [patent_doc_number] => 06343351 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Method and system for the dynamic scheduling of requests to access a storage system' [patent_app_type] => B1 [patent_app_number] => 09/148181 [patent_app_country] => US [patent_app_date] => 1998-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6119 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/343/06343351.pdf [firstpage_image] =>[orig_patent_app_number] => 09148181 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1557237 [patent_doc_number] => 06349362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-02-19 [patent_title] => 'Scheme to partition a large lookaside buffer into an L2 cache array' [patent_app_type] => B2 [patent_app_number] => 09/143794 [patent_app_country] => US [patent_app_date] => 1998-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5642 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/349/06349362.pdf [firstpage_image] =>[orig_patent_app_number] => 09143794 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4350710 [patent_doc_number] => 06334167 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'System and method for memory self-timed refresh for reduced power consumption' [patent_app_type] => 1 [patent_app_number] => 9/144593 [patent_app_country] => US [patent_app_date] => 1998-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1970 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/334/06334167.pdf [firstpage_image] =>[orig_patent_app_number] => 144593 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4373978 [patent_doc_number] => 06292869 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'System and method for memory scrub during self timed refresh' [patent_app_type] => 1 [patent_app_number] => 9/144248 [patent_app_country] => US [patent_app_date] => 1998-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2123 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292869.pdf [firstpage_image] =>[orig_patent_app_number] => 144248 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4399143 [patent_doc_number] => 06295576 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Associative memory having a mask function for use in a network router' [patent_app_type] => 1 [patent_app_number] => 9/144066 [patent_app_country] => US [patent_app_date] => 1998-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 15843 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/295/06295576.pdf [firstpage_image] =>[orig_patent_app_number] => 144066 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4422056 [patent_doc_number] => 06233646 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Memory interface controller' [patent_app_type] => 1 [patent_app_number] => 9/143081 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4143 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233646.pdf [firstpage_image] =>[orig_patent_app_number] => 143081 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1540099 [patent_doc_number] => 06338127 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same' [patent_app_type] => B1 [patent_app_number] => 09/143033 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 24451 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/338/06338127.pdf [firstpage_image] =>[orig_patent_app_number] => 09143033 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1120000 [patent_doc_number] => 06801983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-05 [patent_title] => 'Disk control device and storage device using it' [patent_app_type] => B2 [patent_app_number] => 09/141601 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4077 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/801/06801983.pdf [firstpage_image] =>[orig_patent_app_number] => 09141601 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1540056 [patent_doc_number] => 06338117 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'System and method for coordinated hierarchical caching and cache replacement' [patent_app_type] => B1 [patent_app_number] => 09/141979 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9011 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/338/06338117.pdf [firstpage_image] =>[orig_patent_app_number] => 09141979 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4376663 [patent_doc_number] => 06219766 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Method for record-based backward skipping within physical blocks of data' [patent_app_type] => 1 [patent_app_number] => 9/139068 [patent_app_country] => US [patent_app_date] => 1998-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3715 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219766.pdf [firstpage_image] =>[orig_patent_app_number] => 139068 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6001638 [patent_doc_number] => 20020029327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-07 [patent_title] => 'LINKED LIST MEMORY AND METHOD THEREFOR' [patent_app_type] => new [patent_app_number] => 09/138909 [patent_app_country] => US [patent_app_date] => 1998-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6124 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20020029327.pdf [firstpage_image] =>[orig_patent_app_number] => 09138909 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4312289 [patent_doc_number] => 06237072 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Memory management with compaction of data blocks' [patent_app_type] => 1 [patent_app_number] => 9/139203 [patent_app_country] => US [patent_app_date] => 1998-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4332 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/237/06237072.pdf [firstpage_image] =>[orig_patent_app_number] => 139203 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4371187 [patent_doc_number] => 06216210 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Record-based backward skipping within physical blocks of data' [patent_app_type] => 1 [patent_app_number] => 9/138710 [patent_app_country] => US [patent_app_date] => 1998-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3758 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/216/06216210.pdf [firstpage_image] =>[orig_patent_app_number] => 138710 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4376677 [patent_doc_number] => 06219767 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'System for record-based backward skipping within physical blocks of data' [patent_app_type] => 1 [patent_app_number] => 9/139091 [patent_app_country] => US [patent_app_date] => 1998-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3897 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219767.pdf [firstpage_image] =>[orig_patent_app_number] => 139091 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6962840 [patent_doc_number] => 20010013092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-09 [patent_title] => 'MEMORY LATENCY COMPENSATION' [patent_app_type] => new [patent_app_number] => 09/137439 [patent_app_country] => US [patent_app_date] => 1998-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8158 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20010013092.pdf [firstpage_image] =>[orig_patent_app_number] => 09137439 [rel_patent_id] =>[rel_patent_doc_number] =>)