Search

William P Neuder

Examiner (ID: 14991)

Most Active Art Unit
3672
Art Unit(s)
3625, 3642, 3672, 2899, 3506
Total Applications
4583
Issued Applications
4085
Pending Applications
166
Abandoned Applications
332

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4312232 [patent_doc_number] => 06237068 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'System for multi-volume, write-behind data storage in a distributed processing system' [patent_app_type] => 1 [patent_app_number] => 9/136149 [patent_app_country] => US [patent_app_date] => 1998-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 6567 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/237/06237068.pdf [firstpage_image] =>[orig_patent_app_number] => 136149 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/136149
System for multi-volume, write-behind data storage in a distributed processing system Aug 17, 1998 Issued
Array ( [id] => 4371173 [patent_doc_number] => 06216209 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Multi-volume, write-behind data storage in a distributed processing system' [patent_app_type] => 1 [patent_app_number] => 9/135664 [patent_app_country] => US [patent_app_date] => 1998-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 6854 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 397 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/216/06216209.pdf [firstpage_image] =>[orig_patent_app_number] => 135664 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/135664
Multi-volume, write-behind data storage in a distributed processing system Aug 17, 1998 Issued
Array ( [id] => 4270276 [patent_doc_number] => 06223262 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Method for multi-volume, write-behind data storage in a distributed processing system' [patent_app_type] => 1 [patent_app_number] => 9/136052 [patent_app_country] => US [patent_app_date] => 1998-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 6694 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223262.pdf [firstpage_image] =>[orig_patent_app_number] => 136052 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/136052
Method for multi-volume, write-behind data storage in a distributed processing system Aug 17, 1998 Issued
Array ( [id] => 4422545 [patent_doc_number] => 06272609 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Pipelined memory controller' [patent_app_type] => 1 [patent_app_number] => 9/127207 [patent_app_country] => US [patent_app_date] => 1998-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4120 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272609.pdf [firstpage_image] =>[orig_patent_app_number] => 127207 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/127207
Pipelined memory controller Jul 30, 1998 Issued
Array ( [id] => 4422378 [patent_doc_number] => 06272594 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Method and apparatus for determining interleaving schemes in a computer system that supports multiple interleaving schemes' [patent_app_type] => 1 [patent_app_number] => 9/127239 [patent_app_country] => US [patent_app_date] => 1998-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 9160 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272594.pdf [firstpage_image] =>[orig_patent_app_number] => 127239 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/127239
Method and apparatus for determining interleaving schemes in a computer system that supports multiple interleaving schemes Jul 30, 1998 Issued
Array ( [id] => 4399360 [patent_doc_number] => 06295592 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Method of processing memory requests in a pipelined memory controller' [patent_app_type] => 1 [patent_app_number] => 9/127282 [patent_app_country] => US [patent_app_date] => 1998-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4122 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/295/06295592.pdf [firstpage_image] =>[orig_patent_app_number] => 127282 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/127282
Method of processing memory requests in a pipelined memory controller Jul 30, 1998 Issued
Array ( [id] => 6143552 [patent_doc_number] => 20020002660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'MULTIPLE CACHE COMMUNICATION' [patent_app_type] => new [patent_app_number] => 09/127249 [patent_app_country] => US [patent_app_date] => 1998-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5100 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 22 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20020002660.pdf [firstpage_image] =>[orig_patent_app_number] => 09127249 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/127249
Multiple cache communication Jul 30, 1998 Issued
Array ( [id] => 4273713 [patent_doc_number] => 06209076 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Method and apparatus for two-stage address generation' [patent_app_type] => 1 [patent_app_number] => 9/122504 [patent_app_country] => US [patent_app_date] => 1998-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4914 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/209/06209076.pdf [firstpage_image] =>[orig_patent_app_number] => 122504 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/122504
Method and apparatus for two-stage address generation Jul 23, 1998 Issued
Array ( [id] => 1206856 [patent_doc_number] => 06721844 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-13 [patent_title] => 'Data storage unit and method for starting data storage unit' [patent_app_type] => B1 [patent_app_number] => 09/114584 [patent_app_country] => US [patent_app_date] => 1998-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4726 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/721/06721844.pdf [firstpage_image] =>[orig_patent_app_number] => 09114584 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/114584
Data storage unit and method for starting data storage unit Jul 12, 1998 Issued
Array ( [id] => 4280715 [patent_doc_number] => 06260108 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'System and method for modeling and optimizing I/O throughput of multiple disks on a bus' [patent_app_type] => 1 [patent_app_number] => 9/110114 [patent_app_country] => US [patent_app_date] => 1998-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 7428 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260108.pdf [firstpage_image] =>[orig_patent_app_number] => 110114 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/110114
System and method for modeling and optimizing I/O throughput of multiple disks on a bus Jul 1, 1998 Issued
Array ( [id] => 6962804 [patent_doc_number] => 20010013084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-09 [patent_title] => 'SYSTEM AND METHOD FOR MODELING AND OPTIMIZING I/O THROUGHPUT OF MULTIPLE DISKS ON A BUS' [patent_app_type] => new [patent_app_number] => 09/110110 [patent_app_country] => US [patent_app_date] => 1998-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7721 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20010013084.pdf [firstpage_image] =>[orig_patent_app_number] => 09110110 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/110110
System and method for modeling and optimizing I/O throughput of multiple disks on a bus Jul 1, 1998 Issued
Array ( [id] => 4388288 [patent_doc_number] => 06275912 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Method and system for storing data items to a storage device' [patent_app_type] => 1 [patent_app_number] => 9/114228 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4761 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275912.pdf [firstpage_image] =>[orig_patent_app_number] => 114228 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/114228
Method and system for storing data items to a storage device Jun 29, 1998 Issued
Array ( [id] => 4325241 [patent_doc_number] => 06253276 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Apparatus for adaptive decoding of memory addresses' [patent_app_type] => 1 [patent_app_number] => 9/107782 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2603 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/253/06253276.pdf [firstpage_image] =>[orig_patent_app_number] => 107782 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/107782
Apparatus for adaptive decoding of memory addresses Jun 29, 1998 Issued
Array ( [id] => 4280649 [patent_doc_number] => 06260104 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Multiplexing of trim outputs on a trim bus to reduce die size' [patent_app_type] => 1 [patent_app_number] => 9/107062 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3280 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260104.pdf [firstpage_image] =>[orig_patent_app_number] => 107062 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/107062
Multiplexing of trim outputs on a trim bus to reduce die size Jun 29, 1998 Issued
Array ( [id] => 1438682 [patent_doc_number] => 06356984 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Digital data processing system having a data bus and a control bus' [patent_app_type] => B1 [patent_app_number] => 09/107070 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 19582 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356984.pdf [firstpage_image] =>[orig_patent_app_number] => 09107070 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/107070
Digital data processing system having a data bus and a control bus Jun 29, 1998 Issued
Array ( [id] => 6908572 [patent_doc_number] => 20010011339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-02 [patent_title] => 'METHOD AND APPARATUS FOR PRODUCT DEVELOPMENT' [patent_app_type] => new [patent_app_number] => 09/106880 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3182 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20010011339.pdf [firstpage_image] =>[orig_patent_app_number] => 09106880 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/106880
Method and apparatus for product development Jun 29, 1998 Issued
Array ( [id] => 4280906 [patent_doc_number] => 06260121 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method for adaptive decoding of memory addresses' [patent_app_type] => 1 [patent_app_number] => 9/106967 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2887 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260121.pdf [firstpage_image] =>[orig_patent_app_number] => 106967 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/106967
Method for adaptive decoding of memory addresses Jun 29, 1998 Issued
Array ( [id] => 4290227 [patent_doc_number] => 06308242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Apparatus for adaptively controlling a prefetch queue based on various flush conditions' [patent_app_type] => 1 [patent_app_number] => 9/104542 [patent_app_country] => US [patent_app_date] => 1998-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2214 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/308/06308242.pdf [firstpage_image] =>[orig_patent_app_number] => 104542 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/104542
Apparatus for adaptively controlling a prefetch queue based on various flush conditions Jun 25, 1998 Issued
Array ( [id] => 4404001 [patent_doc_number] => 06263412 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Method and apparatus for RAM emulation using a processor register set' [patent_app_type] => 1 [patent_app_number] => 9/104937 [patent_app_country] => US [patent_app_date] => 1998-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 2908 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/263/06263412.pdf [firstpage_image] =>[orig_patent_app_number] => 104937 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/104937
Method and apparatus for RAM emulation using a processor register set Jun 23, 1998 Issued
Array ( [id] => 4310227 [patent_doc_number] => 06212608 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Method and apparatus for thread synchronization in an object-based system' [patent_app_type] => 1 [patent_app_number] => 9/102980 [patent_app_country] => US [patent_app_date] => 1998-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6545 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212608.pdf [firstpage_image] =>[orig_patent_app_number] => 102980 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/102980
Method and apparatus for thread synchronization in an object-based system Jun 21, 1998 Issued
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