Search

William P Neuder

Examiner (ID: 14991)

Most Active Art Unit
3672
Art Unit(s)
3625, 3642, 3672, 2899, 3506
Total Applications
4583
Issued Applications
4085
Pending Applications
166
Abandoned Applications
332

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1284542 [patent_doc_number] => 06651144 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Method and apparatus for developing multiprocessor cache control protocols using an external acknowledgement signal to set a cache to a dirty state' [patent_app_type] => B1 [patent_app_number] => 09/099384 [patent_app_country] => US [patent_app_date] => 1998-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 8415 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/651/06651144.pdf [firstpage_image] =>[orig_patent_app_number] => 09099384 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/099384
Method and apparatus for developing multiprocessor cache control protocols using an external acknowledgement signal to set a cache to a dirty state Jun 17, 1998 Issued
Array ( [id] => 6922157 [patent_doc_number] => 20010029574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-11 [patent_title] => 'METHOD AND APPARATUS FOR DEVELOPING MULTIPROCESSORE CACHE CONTROL PROTOCOLS USING A MEMORY MANAGEMENT SYSTEM GENERATING AN EXTERNAL ACKNOWLEDGEMENT SIGNAL TO SET A CACHE TO A DIRTY COHERENCE STATE' [patent_app_type] => new [patent_app_number] => 09/099386 [patent_app_country] => US [patent_app_date] => 1998-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8154 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20010029574.pdf [firstpage_image] =>[orig_patent_app_number] => 09099386 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/099386
METHOD AND APPARATUS FOR DEVELOPING MULTIPROCESSORE CACHE CONTROL PROTOCOLS USING A MEMORY MANAGEMENT SYSTEM GENERATING AN EXTERNAL ACKNOWLEDGEMENT SIGNAL TO SET A CACHE TO A DIRTY COHERENCE STATE Jun 17, 1998 Abandoned
Array ( [id] => 4351869 [patent_doc_number] => 06314496 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Method and apparatus for developing multiprocessor cache control protocols using atomic probe commands and system data control response commands' [patent_app_type] => 1 [patent_app_number] => 9/099398 [patent_app_country] => US [patent_app_date] => 1998-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 8893 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/314/06314496.pdf [firstpage_image] =>[orig_patent_app_number] => 099398 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/099398
Method and apparatus for developing multiprocessor cache control protocols using atomic probe commands and system data control response commands Jun 17, 1998 Issued
Array ( [id] => 7118679 [patent_doc_number] => 20010001872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-24 [patent_title] => 'DATA CACHING WITH A PARTIALLY COMPRESSED CACHE' [patent_app_type] => new-utility [patent_app_number] => 09/090028 [patent_app_country] => US [patent_app_date] => 1998-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4163 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20010001872.pdf [firstpage_image] =>[orig_patent_app_number] => 09090028 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/090028
Data caching with a partially compressed cache Jun 9, 1998 Issued
Array ( [id] => 4292370 [patent_doc_number] => 06247108 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Memory management during processing of binary decision diagrams in a computer system' [patent_app_type] => 1 [patent_app_number] => 9/089835 [patent_app_country] => US [patent_app_date] => 1998-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4376 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247108.pdf [firstpage_image] =>[orig_patent_app_number] => 089835 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/089835
Memory management during processing of binary decision diagrams in a computer system Jun 2, 1998 Issued
Array ( [id] => 4176746 [patent_doc_number] => 06157989 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Dynamic bus arbitration priority and task switching based on shared memory fullness in a multi-processor system' [patent_app_type] => 1 [patent_app_number] => 9/089721 [patent_app_country] => US [patent_app_date] => 1998-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4640 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157989.pdf [firstpage_image] =>[orig_patent_app_number] => 089721 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/089721
Dynamic bus arbitration priority and task switching based on shared memory fullness in a multi-processor system Jun 2, 1998 Issued
Array ( [id] => 4366305 [patent_doc_number] => 06286090 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetches' [patent_app_type] => 1 [patent_app_number] => 9/084621 [patent_app_country] => US [patent_app_date] => 1998-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 10121 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/286/06286090.pdf [firstpage_image] =>[orig_patent_app_number] => 084621 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/084621
Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetches May 25, 1998 Issued
Array ( [id] => 4270101 [patent_doc_number] => 06223252 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Hot spare light weight mirror for raid system' [patent_app_type] => 1 [patent_app_number] => 9/072259 [patent_app_country] => US [patent_app_date] => 1998-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3947 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223252.pdf [firstpage_image] =>[orig_patent_app_number] => 072259 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/072259
Hot spare light weight mirror for raid system May 3, 1998 Issued
Array ( [id] => 1214427 [patent_doc_number] => 06715056 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Network document transmission to receiving display stations with automatic sizing of received document caches based upon user activity in prior browsing sessions' [patent_app_type] => B1 [patent_app_number] => 09/070039 [patent_app_country] => US [patent_app_date] => 1998-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3968 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/715/06715056.pdf [firstpage_image] =>[orig_patent_app_number] => 09070039 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/070039
Network document transmission to receiving display stations with automatic sizing of received document caches based upon user activity in prior browsing sessions Apr 29, 1998 Issued
Array ( [id] => 4325409 [patent_doc_number] => 06253288 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Hybrid cache/SIRO buffer system' [patent_app_type] => 1 [patent_app_number] => 9/070190 [patent_app_country] => US [patent_app_date] => 1998-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 6087 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/253/06253288.pdf [firstpage_image] =>[orig_patent_app_number] => 070190 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/070190
Hybrid cache/SIRO buffer system Apr 29, 1998 Issued
Array ( [id] => 4260325 [patent_doc_number] => 06167494 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Method and system for recovering from operating system failure' [patent_app_type] => 1 [patent_app_number] => 9/067630 [patent_app_country] => US [patent_app_date] => 1998-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3273 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/167/06167494.pdf [firstpage_image] =>[orig_patent_app_number] => 067630 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/067630
Method and system for recovering from operating system failure Apr 27, 1998 Issued
Array ( [id] => 4374169 [patent_doc_number] => 06292880 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Alias-free content-indexed object cache' [patent_app_type] => 1 [patent_app_number] => 9/060886 [patent_app_country] => US [patent_app_date] => 1998-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 27 [patent_no_of_words] => 23470 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292880.pdf [firstpage_image] =>[orig_patent_app_number] => 060886 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/060886
Alias-free content-indexed object cache Apr 14, 1998 Issued
Array ( [id] => 1567451 [patent_doc_number] => 06363463 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Method and apparatus for protecting flash memory' [patent_app_type] => B1 [patent_app_number] => 09/060679 [patent_app_country] => US [patent_app_date] => 1998-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5827 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363463.pdf [firstpage_image] =>[orig_patent_app_number] => 09060679 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/060679
Method and apparatus for protecting flash memory Apr 14, 1998 Issued
Array ( [id] => 6780013 [patent_doc_number] => 20030051095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-13 [patent_title] => 'METHOD AND DEVICE FOR OBTAINING AN ADAPTIVE SELECTION OF SETS OF DATA STORED IN A MASS MEMORY' [patent_app_type] => new [patent_app_number] => 09/055343 [patent_app_country] => US [patent_app_date] => 1998-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4732 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20030051095.pdf [firstpage_image] =>[orig_patent_app_number] => 09055343 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/055343
Method and device for obtaining an adaptive selection of sets of data stored in a mass memory Apr 5, 1998 Issued
Array ( [id] => 7633086 [patent_doc_number] => 06658534 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Mechanism to reduce instruction cache miss penalties and methods therefor' [patent_app_type] => B1 [patent_app_number] => 09/052247 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4828 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/658/06658534.pdf [firstpage_image] =>[orig_patent_app_number] => 09052247 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/052247
Mechanism to reduce instruction cache miss penalties and methods therefor Mar 30, 1998 Issued
Array ( [id] => 4273624 [patent_doc_number] => 06209070 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'System for multiple data transfer operations' [patent_app_type] => 1 [patent_app_number] => 9/045138 [patent_app_country] => US [patent_app_date] => 1998-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4471 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/209/06209070.pdf [firstpage_image] =>[orig_patent_app_number] => 045138 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/045138
System for multiple data transfer operations Mar 19, 1998 Issued
Array ( [id] => 4317846 [patent_doc_number] => 06182191 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Recording and reproducing system' [patent_app_type] => 1 [patent_app_number] => 9/031069 [patent_app_country] => US [patent_app_date] => 1998-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 8496 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/182/06182191.pdf [firstpage_image] =>[orig_patent_app_number] => 031069 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/031069
Recording and reproducing system Feb 25, 1998 Issued
Array ( [id] => 4317815 [patent_doc_number] => 06185665 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'File management apparatus, file management method, and recording medium containing file management program' [patent_app_type] => 1 [patent_app_number] => 9/030373 [patent_app_country] => US [patent_app_date] => 1998-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 27 [patent_no_of_words] => 17787 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185665.pdf [firstpage_image] =>[orig_patent_app_number] => 030373 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/030373
File management apparatus, file management method, and recording medium containing file management program Feb 24, 1998 Issued
Array ( [id] => 5952969 [patent_doc_number] => 20020007433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-17 [patent_title] => 'APPARATUS AND METHOD FOR DATA PROCESSING EMPLOYING DATA BLOCKS AND UPDATING BLOCKS' [patent_app_type] => new [patent_app_number] => 09/027577 [patent_app_country] => US [patent_app_date] => 1998-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 20034 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20020007433.pdf [firstpage_image] =>[orig_patent_app_number] => 09027577 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/027577
Apparatus and method for data processing employing data blocks and updating blocks Feb 22, 1998 Issued
Array ( [id] => 4312174 [patent_doc_number] => 06237064 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Cache memory with reduced latency' [patent_app_type] => 1 [patent_app_number] => 9/027539 [patent_app_country] => US [patent_app_date] => 1998-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2725 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/237/06237064.pdf [firstpage_image] =>[orig_patent_app_number] => 027539 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/027539
Cache memory with reduced latency Feb 22, 1998 Issued
Menu