Search

William P Neuder

Examiner (ID: 14991)

Most Active Art Unit
3672
Art Unit(s)
3625, 3642, 3672, 2899, 3506
Total Applications
4583
Issued Applications
4085
Pending Applications
166
Abandoned Applications
332

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4374171 [patent_doc_number] => 06175903 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Duplexing system and method for writing reserve list thereof' [patent_app_type] => 1 [patent_app_number] => 9/026597 [patent_app_country] => US [patent_app_date] => 1998-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 4980 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175903.pdf [firstpage_image] =>[orig_patent_app_number] => 026597 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/026597
Duplexing system and method for writing reserve list thereof Feb 19, 1998 Issued
Array ( [id] => 4422318 [patent_doc_number] => 06173356 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Multi-port DRAM with integrated SRAM and systems and methods using the same' [patent_app_type] => 1 [patent_app_number] => 9/026927 [patent_app_country] => US [patent_app_date] => 1998-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 12153 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/173/06173356.pdf [firstpage_image] =>[orig_patent_app_number] => 026927 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/026927
Multi-port DRAM with integrated SRAM and systems and methods using the same Feb 19, 1998 Issued
Array ( [id] => 1557311 [patent_doc_number] => 06349373 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-02-19 [patent_title] => 'Digital image management system having method for managing images according to image groups' [patent_app_type] => B2 [patent_app_number] => 09/026986 [patent_app_country] => US [patent_app_date] => 1998-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4392 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/349/06349373.pdf [firstpage_image] =>[orig_patent_app_number] => 09026986 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/026986
Digital image management system having method for managing images according to image groups Feb 19, 1998 Issued
Array ( [id] => 1460034 [patent_doc_number] => 06463514 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Method to arbitrate for a cache block' [patent_app_type] => B1 [patent_app_number] => 09/025605 [patent_app_country] => US [patent_app_date] => 1998-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3786 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463514.pdf [firstpage_image] =>[orig_patent_app_number] => 09025605 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/025605
Method to arbitrate for a cache block Feb 17, 1998 Issued
Array ( [id] => 1434046 [patent_doc_number] => 06341336 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Cache coherency protocol having tagged state used with cross-bars' [patent_app_type] => B1 [patent_app_number] => 09/024676 [patent_app_country] => US [patent_app_date] => 1998-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 10322 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/341/06341336.pdf [firstpage_image] =>[orig_patent_app_number] => 09024676 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/024676
Cache coherency protocol having tagged state used with cross-bars Feb 16, 1998 Issued
Array ( [id] => 4346361 [patent_doc_number] => 06330643 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Cache coherency protocols with global and local posted operations' [patent_app_type] => 1 [patent_app_number] => 9/024385 [patent_app_country] => US [patent_app_date] => 1998-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 8633 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/330/06330643.pdf [firstpage_image] =>[orig_patent_app_number] => 024385 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/024385
Cache coherency protocols with global and local posted operations Feb 16, 1998 Issued
Array ( [id] => 4350787 [patent_doc_number] => 06334172 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Cache coherency protocol with tagged state for modified values' [patent_app_type] => 1 [patent_app_number] => 9/024393 [patent_app_country] => US [patent_app_date] => 1998-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 10476 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/334/06334172.pdf [firstpage_image] =>[orig_patent_app_number] => 024393 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/024393
Cache coherency protocol with tagged state for modified values Feb 16, 1998 Issued
Array ( [id] => 4403830 [patent_doc_number] => 06263398 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Integrated circuit memory device incorporating a non-volatile memory array and a relatively faster access time memory cache' [patent_app_type] => 1 [patent_app_number] => 9/021132 [patent_app_country] => US [patent_app_date] => 1998-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 6748 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/263/06263398.pdf [firstpage_image] =>[orig_patent_app_number] => 021132 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/021132
Integrated circuit memory device incorporating a non-volatile memory array and a relatively faster access time memory cache Feb 9, 1998 Issued
Array ( [id] => 4424134 [patent_doc_number] => 06301645 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'System for issuing device requests by proxy' [patent_app_type] => 1 [patent_app_number] => 9/008899 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2824 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301645.pdf [firstpage_image] =>[orig_patent_app_number] => 008899 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/008899
System for issuing device requests by proxy Jan 19, 1998 Issued
Array ( [id] => 4349694 [patent_doc_number] => 06321307 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Computer system and method employing speculative snooping for optimizing performance' [patent_app_type] => 1 [patent_app_number] => 9/001528 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6787 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321307.pdf [firstpage_image] =>[orig_patent_app_number] => 001528 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001528
Computer system and method employing speculative snooping for optimizing performance Dec 30, 1997 Issued
Array ( [id] => 4388355 [patent_doc_number] => 06275916 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Object oriented program memory management system and method using fixed sized memory pools' [patent_app_type] => 1 [patent_app_number] => 8/993942 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 3228 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275916.pdf [firstpage_image] =>[orig_patent_app_number] => 993942 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/993942
Object oriented program memory management system and method using fixed sized memory pools Dec 17, 1997 Issued
Array ( [id] => 4257518 [patent_doc_number] => 06145052 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Disk drive with adaptive pooling for command reordering' [patent_app_type] => 1 [patent_app_number] => 8/963772 [patent_app_country] => US [patent_app_date] => 1997-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 5 [patent_no_of_words] => 4905 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/145/06145052.pdf [firstpage_image] =>[orig_patent_app_number] => 963772 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/963772
Disk drive with adaptive pooling for command reordering Nov 3, 1997 Issued
Array ( [id] => 4177587 [patent_doc_number] => 06108745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Fast and compact address bit routing scheme that supports various DRAM bank sizes and multiple interleaving schemes' [patent_app_type] => 1 [patent_app_number] => 8/962490 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 9904 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108745.pdf [firstpage_image] =>[orig_patent_app_number] => 962490 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/962490
Fast and compact address bit routing scheme that supports various DRAM bank sizes and multiple interleaving schemes Oct 30, 1997 Issued
08/848970 RESILIENT LINKS TO DATA May 1, 1997 Abandoned
Array ( [id] => 4323869 [patent_doc_number] => 06189074 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Mechanism for storing system level attributes in a translation lookaside buffer' [patent_app_type] => 1 [patent_app_number] => 8/820965 [patent_app_country] => US [patent_app_date] => 1997-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5173 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/189/06189074.pdf [firstpage_image] =>[orig_patent_app_number] => 820965 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/820965
Mechanism for storing system level attributes in a translation lookaside buffer Mar 18, 1997 Issued
Array ( [id] => 4280607 [patent_doc_number] => 06260101 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Microcontroller having dedicated hardware for memory address space expansion supporting both static and dynamic memory devices' [patent_app_type] => 1 [patent_app_number] => 8/813620 [patent_app_country] => US [patent_app_date] => 1997-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 13670 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260101.pdf [firstpage_image] =>[orig_patent_app_number] => 813620 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/813620
Microcontroller having dedicated hardware for memory address space expansion supporting both static and dynamic memory devices Mar 6, 1997 Issued
Array ( [id] => 4374048 [patent_doc_number] => 06175894 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Memory device command buffer apparatus and method and memory devices and computer systems using same' [patent_app_type] => 1 [patent_app_number] => 8/813041 [patent_app_country] => US [patent_app_date] => 1997-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 9318 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175894.pdf [firstpage_image] =>[orig_patent_app_number] => 813041 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/813041
Memory device command buffer apparatus and method and memory devices and computer systems using same Mar 4, 1997 Issued
Array ( [id] => 4335248 [patent_doc_number] => 06243797 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Multiplexed semiconductor data transfer arrangement with timing signal generator' [patent_app_type] => 1 [patent_app_number] => 8/801161 [patent_app_country] => US [patent_app_date] => 1997-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10105 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243797.pdf [firstpage_image] =>[orig_patent_app_number] => 801161 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/801161
Multiplexed semiconductor data transfer arrangement with timing signal generator Feb 17, 1997 Issued
Array ( [id] => 4109889 [patent_doc_number] => 06134627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Thread synchronization in a computer controlled by an object-based program' [patent_app_type] => 1 [patent_app_number] => 8/743484 [patent_app_country] => US [patent_app_date] => 1996-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3074 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134627.pdf [firstpage_image] =>[orig_patent_app_number] => 743484 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/743484
Thread synchronization in a computer controlled by an object-based program Nov 3, 1996 Issued
Array ( [id] => 4422546 [patent_doc_number] => 06173376 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Data backup and restore method and system in a multisystem environment' [patent_app_type] => 1 [patent_app_number] => 8/725793 [patent_app_country] => US [patent_app_date] => 1996-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3408 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/173/06173376.pdf [firstpage_image] =>[orig_patent_app_number] => 725793 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/725793
Data backup and restore method and system in a multisystem environment Oct 2, 1996 Issued
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