William P Neuder
Examiner (ID: 14991)
Most Active Art Unit | 3672 |
Art Unit(s) | 3625, 3642, 3672, 2899, 3506 |
Total Applications | 4583 |
Issued Applications | 4085 |
Pending Applications | 166 |
Abandoned Applications | 332 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 971391
[patent_doc_number] => 06941435
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-09-06
[patent_title] => 'Integrated circuit having register configuration sets'
[patent_app_type] => utility
[patent_app_number] => 10/248454
[patent_app_country] => US
[patent_app_date] => 2003-01-21
[patent_effective_date] => 0000-00-00
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/941/06941435.pdf
[firstpage_image] =>[orig_patent_app_number] => 10248454
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/248454 | Integrated circuit having register configuration sets | Jan 20, 2003 | Issued |
Array
(
[id] => 6698165
[patent_doc_number] => 20030110359
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-12
[patent_title] => 'Method and apparatus for altering data length to zero to maintain cache coherency'
[patent_app_type] => new
[patent_app_number] => 10/346060
[patent_app_country] => US
[patent_app_date] => 2003-01-17
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0110/20030110359.pdf
[firstpage_image] =>[orig_patent_app_number] => 10346060
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/346060 | Method and apparatus for altering data length to zero to maintain cache coherency | Jan 16, 2003 | Issued |
Array
(
[id] => 7391652
[patent_doc_number] => 20040083338
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-29
[patent_title] => 'Disk array controller'
[patent_app_type] => new
[patent_app_number] => 10/341446
[patent_app_country] => US
[patent_app_date] => 2003-01-14
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0083/20040083338.pdf
[firstpage_image] =>[orig_patent_app_number] => 10341446
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/341446 | Scalable disk array controller inter-connection network | Jan 13, 2003 | Issued |
Array
(
[id] => 7445067
[patent_doc_number] => 20040003176
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[patent_kind] => A1
[patent_issue_date] => 2004-01-01
[patent_title] => 'Storage device and cache memory device in set associative system'
[patent_app_type] => new
[patent_app_number] => 10/341456
[patent_app_country] => US
[patent_app_date] => 2003-01-14
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 6506
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[firstpage_image] =>[orig_patent_app_number] => 10341456
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/341456 | Storage device and cache memory device in set associative system | Jan 13, 2003 | Issued |
Array
(
[id] => 7328701
[patent_doc_number] => 20040139294
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-15
[patent_title] => 'Backup firmware in a distributed system'
[patent_app_type] => new
[patent_app_number] => 10/341377
[patent_app_country] => US
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[pdf_file] => publications/A1/0139/20040139294.pdf
[firstpage_image] =>[orig_patent_app_number] => 10341377
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/341377 | Backup firmware in a distributed system | Jan 13, 2003 | Issued |
Array
(
[id] => 7328702
[patent_doc_number] => 20040139295
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-15
[patent_title] => 'Acceleration of input/output (I/O) communication through improved address translation'
[patent_app_type] => new
[patent_app_number] => 10/339766
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/339766 | Acceleration of input/output (I/O) communication through improved address translation | Jan 8, 2003 | Issued |
Array
(
[id] => 7621152
[patent_doc_number] => 06978349
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[patent_kind] => B1
[patent_issue_date] => 2005-12-20
[patent_title] => 'Adaptive cache memory management'
[patent_app_type] => utility
[patent_app_number] => 10/339206
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[patent_app_date] => 2003-01-09
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/978/06978349.pdf
[firstpage_image] =>[orig_patent_app_number] => 10339206
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/339206 | Adaptive cache memory management | Jan 8, 2003 | Issued |
Array
(
[id] => 1004671
[patent_doc_number] => 06910110
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[patent_kind] => B2
[patent_issue_date] => 2005-06-21
[patent_title] => 'Interleaving apparatus and method for a communication system'
[patent_app_type] => utility
[patent_app_number] => 10/338715
[patent_app_country] => US
[patent_app_date] => 2003-01-09
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/910/06910110.pdf
[firstpage_image] =>[orig_patent_app_number] => 10338715
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/338715 | Interleaving apparatus and method for a communication system | Jan 8, 2003 | Issued |
Array
(
[id] => 947629
[patent_doc_number] => 06965964
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-11-15
[patent_title] => 'Nand flash memory device'
[patent_app_type] => utility
[patent_app_number] => 10/340359
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[pdf_file] => patents/06/965/06965964.pdf
[firstpage_image] =>[orig_patent_app_number] => 10340359
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/340359 | Nand flash memory device | Jan 8, 2003 | Issued |
Array
(
[id] => 981610
[patent_doc_number] => 06931497
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-16
[patent_title] => 'Shared memory management utilizing a free list of buffer indices'
[patent_app_type] => utility
[patent_app_number] => 10/340078
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[patent_app_date] => 2003-01-09
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[pdf_file] => patents/06/931/06931497.pdf
[firstpage_image] =>[orig_patent_app_number] => 10340078
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/340078 | Shared memory management utilizing a free list of buffer indices | Jan 8, 2003 | Issued |
Array
(
[id] => 7328676
[patent_doc_number] => 20040139287
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[patent_kind] => A1
[patent_issue_date] => 2004-07-15
[patent_title] => 'Method, system, and computer program product for creating and managing memory affinity in logically partitioned data processing systems'
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[patent_app_number] => 10/339774
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/339774 | Method, system, and computer program product for creating and managing memory affinity in logically partitioned data processing systems | Jan 8, 2003 | Issued |
Array
(
[id] => 7293433
[patent_doc_number] => 20040111579
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-06-10
[patent_title] => 'Apparatus and method for memory device block movement'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/338246 | Apparatus and method for memory device block movement | Jan 7, 2003 | Abandoned |
Array
(
[id] => 765162
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[patent_title] => 'Integrated circuit memory device supporting an N bit prefetch scheme and a 2N burst length'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/338398 | Integrated circuit memory device supporting an N bit prefetch scheme and a 2N burst length | Jan 7, 2003 | Issued |
Array
(
[id] => 6844504
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[patent_title] => 'Nonvolatile memory system'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/337314 | Nonvolatile memory system | Jan 6, 2003 | Abandoned |
Array
(
[id] => 950074
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[patent_title] => 'Memory paging based on memory pressure and probability of use of pages'
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Array
(
[id] => 6836092
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[patent_issue_date] => 2003-08-28
[patent_title] => 'Information reproducing apparatus, data management information obtaining method, data management information obtaining program, and storage medium'
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[patent_app_number] => 10/337269
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Array
(
[id] => 984628
[patent_doc_number] => 06928522
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[patent_title] => 'Unbalanced inclusive tags'
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[firstpage_image] =>[orig_patent_app_number] => 10337607
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/337607 | Unbalanced inclusive tags | Jan 6, 2003 | Issued |
Array
(
[id] => 999041
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Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/336708 | Replacement algorithm for a replicated fully associative translation look-aside buffer | Jan 5, 2003 | Issued |