Search

William P Neuder

Examiner (ID: 14991)

Most Active Art Unit
3672
Art Unit(s)
3625, 3642, 3672, 2899, 3506
Total Applications
4583
Issued Applications
4085
Pending Applications
166
Abandoned Applications
332

Applications

Application numberTitle of the applicationFiling DateStatus
10/034286 Initializing selected extents of a storage device Dec 27, 2001 Abandoned
Array ( [id] => 6348872 [patent_doc_number] => 20020035672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-21 [patent_title] => 'System and method for coordinated hierarchical caching and cache replacement' [patent_app_type] => new [patent_app_number] => 09/993837 [patent_app_country] => US [patent_app_date] => 2001-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9092 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20020035672.pdf [firstpage_image] =>[orig_patent_app_number] => 09993837 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/993837
System and method for coordinated hierarchical caching and cache replacement Nov 5, 2001 Issued
Array ( [id] => 6294354 [patent_doc_number] => 20020056032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Pipelined multi-access memory apparatus and method' [patent_app_type] => new [patent_app_number] => 10/002449 [patent_app_country] => US [patent_app_date] => 2001-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10529 [patent_no_of_claims] => 87 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20020056032.pdf [firstpage_image] =>[orig_patent_app_number] => 10002449 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/002449
Pipelined multi-access memory apparatus and method Nov 1, 2001 Issued
Array ( [id] => 7474278 [patent_doc_number] => 20040103243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-27 [patent_title] => 'Apparatus and methods for dedicated command port in memory controllers' [patent_app_type] => new [patent_app_number] => 09/971196 [patent_app_country] => US [patent_app_date] => 2001-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7095 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20040103243.pdf [firstpage_image] =>[orig_patent_app_number] => 09971196 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/971196
Apparatus and methods for dedicated command port in memory controllers Oct 3, 2001 Issued
Array ( [id] => 1314489 [patent_doc_number] => 06622228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-16 [patent_title] => 'System and method of processing memory requests in a pipelined memory controller' [patent_app_type] => B2 [patent_app_number] => 09/931728 [patent_app_country] => US [patent_app_date] => 2001-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4150 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/622/06622228.pdf [firstpage_image] =>[orig_patent_app_number] => 09931728 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/931728
System and method of processing memory requests in a pipelined memory controller Aug 15, 2001 Issued
Array ( [id] => 6065770 [patent_doc_number] => 20020032681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-14 [patent_title] => 'Partially-ordered CAMs used in ternary hierarchical address searching/sorting' [patent_app_type] => new [patent_app_number] => 09/929309 [patent_app_country] => US [patent_app_date] => 2001-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10776 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20020032681.pdf [firstpage_image] =>[orig_patent_app_number] => 09929309 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/929309
Partially-ordered CAMs used in ternary hierarchical address searching/sorting Aug 13, 2001 Abandoned
Array ( [id] => 7080120 [patent_doc_number] => 20010042183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-15 [patent_title] => 'System for issuing device requests by proxy' [patent_app_type] => new [patent_app_number] => 09/917977 [patent_app_country] => US [patent_app_date] => 2001-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2843 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20010042183.pdf [firstpage_image] =>[orig_patent_app_number] => 09917977 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/917977
System for issuing device requests by proxy Jul 29, 2001 Issued
Array ( [id] => 7080097 [patent_doc_number] => 20010042174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-15 [patent_title] => 'Method and apparatus for determining interleaving schemes in a computer system that supports multiple interleaving schemes' [patent_app_type] => new [patent_app_number] => 09/910272 [patent_app_country] => US [patent_app_date] => 2001-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9338 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20010042174.pdf [firstpage_image] =>[orig_patent_app_number] => 09910272 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/910272
Method and apparatus for determining interleaving schemes in a computer system that supports multiple interleaving schemes Jul 18, 2001 Issued
Array ( [id] => 6885441 [patent_doc_number] => 20010039606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-08 [patent_title] => 'Pipelined memory controller' [patent_app_type] => new [patent_app_number] => 09/908784 [patent_app_country] => US [patent_app_date] => 2001-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4115 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20010039606.pdf [firstpage_image] =>[orig_patent_app_number] => 09908784 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/908784
Pipelined memory controller Jul 17, 2001 Issued
Array ( [id] => 1456708 [patent_doc_number] => 06457093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-09-24 [patent_title] => 'Circuit and method to control operations of another circuit' [patent_app_type] => B2 [patent_app_number] => 09/901834 [patent_app_country] => US [patent_app_date] => 2001-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3296 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 32 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457093.pdf [firstpage_image] =>[orig_patent_app_number] => 09901834 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/901834
Circuit and method to control operations of another circuit Jul 9, 2001 Issued
Array ( [id] => 989500 [patent_doc_number] => 06922765 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-26 [patent_title] => 'Method of allocating physical memory space having pinned and non-pinned regions' [patent_app_type] => utility [patent_app_number] => 09/886817 [patent_app_country] => US [patent_app_date] => 2001-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4214 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/922/06922765.pdf [firstpage_image] =>[orig_patent_app_number] => 09886817 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/886817
Method of allocating physical memory space having pinned and non-pinned regions Jun 20, 2001 Issued
Array ( [id] => 782194 [patent_doc_number] => 06996662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-07 [patent_title] => 'Content addressable memory array having flexible priority support' [patent_app_type] => utility [patent_app_number] => 09/884797 [patent_app_country] => US [patent_app_date] => 2001-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7343 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/996/06996662.pdf [firstpage_image] =>[orig_patent_app_number] => 09884797 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/884797
Content addressable memory array having flexible priority support Jun 17, 2001 Issued
Array ( [id] => 1602030 [patent_doc_number] => 06385709 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-07 [patent_title] => 'Multiplexed data transfer arrangement including a multi-phase signal generator for latency control' [patent_app_type] => B2 [patent_app_number] => 09/873463 [patent_app_country] => US [patent_app_date] => 2001-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10328 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385709.pdf [firstpage_image] =>[orig_patent_app_number] => 09873463 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/873463
Multiplexed data transfer arrangement including a multi-phase signal generator for latency control Jun 3, 2001 Issued
Array ( [id] => 6889878 [patent_doc_number] => 20010025333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-27 [patent_title] => 'Integrated circuit memory device incorporating a non-volatile memory array and a relatively faster access time memory cache' [patent_app_type] => new [patent_app_number] => 09/864458 [patent_app_country] => US [patent_app_date] => 2001-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6862 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20010025333.pdf [firstpage_image] =>[orig_patent_app_number] => 09864458 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/864458
Integrated circuit memory device incorporating a non-volatile memory array and a relatively faster access time memory cache May 23, 2001 Abandoned
Array ( [id] => 6155886 [patent_doc_number] => 20020146009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-10 [patent_title] => 'High-speed message forwarding lookups for arbitrary length strings using pipelined memories' [patent_app_type] => new [patent_app_number] => 09/827270 [patent_app_country] => US [patent_app_date] => 2001-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5034 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20020146009.pdf [firstpage_image] =>[orig_patent_app_number] => 09827270 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/827270
High-speed message forwarding lookups for arbitrary length strings using pipelined memories Apr 3, 2001 Issued
Array ( [id] => 7148864 [patent_doc_number] => 20050120180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-02 [patent_title] => 'Cache time determination' [patent_app_type] => utility [patent_app_number] => 10/381109 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4342 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20050120180.pdf [firstpage_image] =>[orig_patent_app_number] => 10381109 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/381109
Cache time determination Mar 29, 2001 Abandoned
Array ( [id] => 6890747 [patent_doc_number] => 20010007978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-12 [patent_title] => 'System and method for analyzing wireless communication data' [patent_app_type] => new-utility [patent_app_number] => 09/758815 [patent_app_country] => US [patent_app_date] => 2001-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 18467 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20010007978.pdf [firstpage_image] =>[orig_patent_app_number] => 09758815 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/758815
System and method for analyzing wireless communication data Jan 10, 2001 Issued
Array ( [id] => 6878322 [patent_doc_number] => 20010002477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-31 [patent_title] => 'System for multi-volume, write-behind data storage in a distributed processing system' [patent_app_type] => new-utility [patent_app_number] => 09/746499 [patent_app_country] => US [patent_app_date] => 2000-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6765 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20010002477.pdf [firstpage_image] =>[orig_patent_app_number] => 09746499 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/746499
System for multi-volume, write-behind data storage in a distributed processing system Dec 20, 2000 Issued
Array ( [id] => 5830457 [patent_doc_number] => 20020069324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Scalable storage architecture' [patent_app_type] => new [patent_app_number] => 09/730631 [patent_app_country] => US [patent_app_date] => 2000-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9288 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20020069324.pdf [firstpage_image] =>[orig_patent_app_number] => 09730631 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/730631
Scalable storage architecture Dec 5, 2000 Abandoned
Array ( [id] => 1592342 [patent_doc_number] => 06360304 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Method for multi-volume, write-behind data storage in a distributed processing system' [patent_app_type] => B1 [patent_app_number] => 09/724414 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 6747 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/360/06360304.pdf [firstpage_image] =>[orig_patent_app_number] => 09724414 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/724414
Method for multi-volume, write-behind data storage in a distributed processing system Nov 27, 2000 Issued
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