Search

William Saba

Examiner (ID: 6317)

Most Active Art Unit
1104
Art Unit(s)
1104, 1101
Total Applications
280
Issued Applications
263
Pending Applications
0
Abandoned Applications
17

Applications

Application numberTitle of the applicationFiling DateStatus
06/706155 METHOD AND APPARATUS FOR LIGHT-INDUCED PHOTOLYTIC DEPOSITION Feb 26, 1985 Abandoned
Array ( [id] => 2269195 [patent_doc_number] => 04601096 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-07-22 [patent_title] => 'Method for fabricating buried channel field effect transistor for microwave and millimeter frequencies utilizing molecular beam epitaxy' [patent_app_type] => 1 [patent_app_number] => 6/702482 [patent_app_country] => US [patent_app_date] => 1985-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 5901 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/601/04601096.pdf [firstpage_image] =>[orig_patent_app_number] => 702482 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/702482
Method for fabricating buried channel field effect transistor for microwave and millimeter frequencies utilizing molecular beam epitaxy Feb 18, 1985 Issued
Array ( [id] => 2278684 [patent_doc_number] => 04638552 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-01-27 [patent_title] => 'Method of manufacturing semiconductor substrate' [patent_app_type] => 1 [patent_app_number] => 6/701516 [patent_app_country] => US [patent_app_date] => 1985-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 2854 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/638/04638552.pdf [firstpage_image] =>[orig_patent_app_number] => 701516 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/701516
Method of manufacturing semiconductor substrate Feb 13, 1985 Issued
Array ( [id] => 2228935 [patent_doc_number] => 04631803 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-12-30 [patent_title] => 'Method of fabricating defect free trench isolation devices' [patent_app_type] => 1 [patent_app_number] => 6/701465 [patent_app_country] => US [patent_app_date] => 1985-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2104 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/631/04631803.pdf [firstpage_image] =>[orig_patent_app_number] => 701465 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/701465
Method of fabricating defect free trench isolation devices Feb 13, 1985 Issued
Array ( [id] => 2196647 [patent_doc_number] => 04548658 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-10-22 [patent_title] => 'Growth of lattice-graded epilayers' [patent_app_type] => 1 [patent_app_number] => 6/696438 [patent_app_country] => US [patent_app_date] => 1985-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3585 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/548/04548658.pdf [firstpage_image] =>[orig_patent_app_number] => 696438 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/696438
Growth of lattice-graded epilayers Jan 29, 1985 Issued
Array ( [id] => 2217197 [patent_doc_number] => 04591398 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-05-27 [patent_title] => 'Method for manufacturing a semiconductor device utilizing self-aligned oxide-nitride masking' [patent_app_type] => 1 [patent_app_number] => 6/700707 [patent_app_country] => US [patent_app_date] => 1985-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 2699 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/591/04591398.pdf [firstpage_image] =>[orig_patent_app_number] => 700707 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/700707
Method for manufacturing a semiconductor device utilizing self-aligned oxide-nitride masking Jan 24, 1985 Issued
Array ( [id] => 2262146 [patent_doc_number] => 04592792 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-06-03 [patent_title] => 'Method for forming uniformly thick selective epitaxial silicon' [patent_app_type] => 1 [patent_app_number] => 6/694100 [patent_app_country] => US [patent_app_date] => 1985-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 1901 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/592/04592792.pdf [firstpage_image] =>[orig_patent_app_number] => 694100 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/694100
Method for forming uniformly thick selective epitaxial silicon Jan 22, 1985 Issued
Array ( [id] => 2208058 [patent_doc_number] => 04581814 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-04-15 [patent_title] => 'Process for fabricating dielectrically isolated devices utilizing heating of the polycrystalline support layer to prevent substrate deformation' [patent_app_type] => 1 [patent_app_number] => 6/681270 [patent_app_country] => US [patent_app_date] => 1984-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 14 [patent_no_of_words] => 3431 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/581/04581814.pdf [firstpage_image] =>[orig_patent_app_number] => 681270 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/681270
Process for fabricating dielectrically isolated devices utilizing heating of the polycrystalline support layer to prevent substrate deformation Dec 12, 1984 Issued
06/681704 METHOD OF FABRICATING PATTERNED EPITAXIAL SILICON FILMS AND DEVICES MADE THEREBY Dec 12, 1984 Abandoned
Array ( [id] => 2241564 [patent_doc_number] => 04632712 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-12-30 [patent_title] => 'Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth' [patent_app_type] => 1 [patent_app_number] => 6/678364 [patent_app_country] => US [patent_app_date] => 1984-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2564 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/632/04632712.pdf [firstpage_image] =>[orig_patent_app_number] => 678364 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/678364
Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth Dec 3, 1984 Issued
Array ( [id] => 2216644 [patent_doc_number] => 04578128 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-03-25 [patent_title] => 'Process for forming retrograde dopant distributions utilizing simultaneous outdiffusion of dopants' [patent_app_type] => 1 [patent_app_number] => 6/677636 [patent_app_country] => US [patent_app_date] => 1984-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4690 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/578/04578128.pdf [firstpage_image] =>[orig_patent_app_number] => 677636 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/677636
Process for forming retrograde dopant distributions utilizing simultaneous outdiffusion of dopants Dec 2, 1984 Issued
Array ( [id] => 2230548 [patent_doc_number] => 04567646 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-02-04 [patent_title] => 'Method for fabricating a dielectric isolated integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 6/676988 [patent_app_country] => US [patent_app_date] => 1984-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 3274 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/567/04567646.pdf [firstpage_image] =>[orig_patent_app_number] => 676988 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/676988
Method for fabricating a dielectric isolated integrated circuit device Nov 29, 1984 Issued
Array ( [id] => 2321182 [patent_doc_number] => 04636268 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-01-13 [patent_title] => 'Chemical beam deposition method utilizing alkyl compounds in a carrier gas' [patent_app_type] => 1 [patent_app_number] => 6/676658 [patent_app_country] => US [patent_app_date] => 1984-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1170 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/636/04636268.pdf [firstpage_image] =>[orig_patent_app_number] => 676658 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/676658
Chemical beam deposition method utilizing alkyl compounds in a carrier gas Nov 29, 1984 Issued
Array ( [id] => 2208169 [patent_doc_number] => 04593454 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-06-10 [patent_title] => 'Process for manufacturing an integrated circuit with tantalum silicide connections utilizing self-aligned oxidation' [patent_app_type] => 1 [patent_app_number] => 6/673425 [patent_app_country] => US [patent_app_date] => 1984-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2371 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/593/04593454.pdf [firstpage_image] =>[orig_patent_app_number] => 673425 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/673425
Process for manufacturing an integrated circuit with tantalum silicide connections utilizing self-aligned oxidation Nov 19, 1984 Issued
Array ( [id] => 2252921 [patent_doc_number] => 04592130 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-06-03 [patent_title] => 'Method of fabricating a CCD read only memory utilizing dual-level junction formation' [patent_app_type] => 1 [patent_app_number] => 6/671802 [patent_app_country] => US [patent_app_date] => 1984-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5187 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/592/04592130.pdf [firstpage_image] =>[orig_patent_app_number] => 671802 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/671802
Method of fabricating a CCD read only memory utilizing dual-level junction formation Nov 14, 1984 Issued
Array ( [id] => 2250766 [patent_doc_number] => 04628591 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-12-16 [patent_title] => 'Method for obtaining full oxide isolation of epitaxial islands in silicon utilizing selective oxidation of porous silicon' [patent_app_type] => 1 [patent_app_number] => 6/666698 [patent_app_country] => US [patent_app_date] => 1984-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1371 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/628/04628591.pdf [firstpage_image] =>[orig_patent_app_number] => 666698 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/666698
Method for obtaining full oxide isolation of epitaxial islands in silicon utilizing selective oxidation of porous silicon Oct 30, 1984 Issued
06/657051 METHOD OF MAKING HIGH MOBILITY MULTILAYERED HETEROJUNCTION DEVICE EMPLOYING MODULATED DOPING Oct 2, 1984 Abandoned
Array ( [id] => 2225809 [patent_doc_number] => 04573257 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-03-04 [patent_title] => 'Method of forming self-aligned implanted channel-stop and buried layer utilizing non-single crystal alignment key' [patent_app_type] => 1 [patent_app_number] => 6/650931 [patent_app_country] => US [patent_app_date] => 1984-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 22 [patent_no_of_words] => 5523 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/573/04573257.pdf [firstpage_image] =>[orig_patent_app_number] => 650931 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/650931
Method of forming self-aligned implanted channel-stop and buried layer utilizing non-single crystal alignment key Sep 13, 1984 Issued
Array ( [id] => 2240844 [patent_doc_number] => 04568397 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-02-04 [patent_title] => 'Metalorganic vapor phase epitaxial growth of group II-VI semiconductor materials' [patent_app_type] => 1 [patent_app_number] => 6/649650 [patent_app_country] => US [patent_app_date] => 1984-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4505 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/568/04568397.pdf [firstpage_image] =>[orig_patent_app_number] => 649650 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/649650
Metalorganic vapor phase epitaxial growth of group II-VI semiconductor materials Sep 11, 1984 Issued
Array ( [id] => 2251415 [patent_doc_number] => 04569123 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-02-11 [patent_title] => 'Method of manufacturing a semiconductor device utilizing simultaneous diffusion from an ion implanted polysilicon layer' [patent_app_type] => 1 [patent_app_number] => 6/648367 [patent_app_country] => US [patent_app_date] => 1984-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 6 [patent_no_of_words] => 3437 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/569/04569123.pdf [firstpage_image] =>[orig_patent_app_number] => 648367 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/648367
Method of manufacturing a semiconductor device utilizing simultaneous diffusion from an ion implanted polysilicon layer Sep 6, 1984 Issued
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