| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 2253333
[patent_doc_number] => 04588451
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-05-13
[patent_title] => 'Metal organic chemical vapor deposition of 111-v compounds on silicon'
[patent_app_type] => 1
[patent_app_number] => 6/604835
[patent_app_country] => US
[patent_app_date] => 1984-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 4626
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/588/04588451.pdf
[firstpage_image] =>[orig_patent_app_number] => 604835
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/604835 | Metal organic chemical vapor deposition of 111-v compounds on silicon | Apr 26, 1984 | Issued |
Array
(
[id] => 2187211
[patent_doc_number] => 04532700
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-08-06
[patent_title] => 'Method of manufacturing semiconductor structures having an oxidized porous silicon isolation layer'
[patent_app_type] => 1
[patent_app_number] => 6/604563
[patent_app_country] => US
[patent_app_date] => 1984-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 7
[patent_no_of_words] => 2475
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/532/04532700.pdf
[firstpage_image] =>[orig_patent_app_number] => 604563
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/604563 | Method of manufacturing semiconductor structures having an oxidized porous silicon isolation layer | Apr 26, 1984 | Issued |
Array
(
[id] => 2174189
[patent_doc_number] => 04554726
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-11-26
[patent_title] => 'CMOS Integrated circuit technology utilizing dual implantation of slow and fast diffusing donor ions to form the n-well'
[patent_app_type] => 1
[patent_app_number] => 6/601353
[patent_app_country] => US
[patent_app_date] => 1984-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 11
[patent_no_of_words] => 5216
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/554/04554726.pdf
[firstpage_image] =>[orig_patent_app_number] => 601353
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/601353 | CMOS Integrated circuit technology utilizing dual implantation of slow and fast diffusing donor ions to form the n-well | Apr 16, 1984 | Issued |
Array
(
[id] => 2249937
[patent_doc_number] => 04563807
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-01-14
[patent_title] => 'Method for making semiconductor device utilizing molecular beam epitaxy to form the emitter layers'
[patent_app_type] => 1
[patent_app_number] => 6/596592
[patent_app_country] => US
[patent_app_date] => 1984-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 21
[patent_no_of_words] => 5051
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/563/04563807.pdf
[firstpage_image] =>[orig_patent_app_number] => 596592
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/596592 | Method for making semiconductor device utilizing molecular beam epitaxy to form the emitter layers | Apr 3, 1984 | Issued |
Array
(
[id] => 2225788
[patent_doc_number] => 04573255
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-03-04
[patent_title] => 'Purging: a reliability assurance technique for semiconductor lasers utilizing a purging process'
[patent_app_type] => 1
[patent_app_number] => 6/592285
[patent_app_country] => US
[patent_app_date] => 1984-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 4
[patent_no_of_words] => 4433
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 30
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/573/04573255.pdf
[firstpage_image] =>[orig_patent_app_number] => 592285
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/592285 | Purging: a reliability assurance technique for semiconductor lasers utilizing a purging process | Mar 21, 1984 | Issued |
Array
(
[id] => 2139955
[patent_doc_number] => 04497109
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-02-05
[patent_title] => 'Method of fabricating light-controlled thyristor utilizing selective etching and ion-implantation'
[patent_app_type] => 1
[patent_app_number] => 6/587839
[patent_app_country] => US
[patent_app_date] => 1984-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 1619
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/497/04497109.pdf
[firstpage_image] =>[orig_patent_app_number] => 587839
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/587839 | Method of fabricating light-controlled thyristor utilizing selective etching and ion-implantation | Mar 11, 1984 | Issued |
Array
(
[id] => 2164118
[patent_doc_number] => 04540452
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-09-10
[patent_title] => 'Process for manufacturing a semi-conductor device of the type comprising at least one silicon layer deposited on an insulating substrate'
[patent_app_type] => 1
[patent_app_number] => 6/587641
[patent_app_country] => US
[patent_app_date] => 1984-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 3292
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 223
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/540/04540452.pdf
[firstpage_image] =>[orig_patent_app_number] => 587641
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/587641 | Process for manufacturing a semi-conductor device of the type comprising at least one silicon layer deposited on an insulating substrate | Mar 7, 1984 | Issued |
Array
(
[id] => 2157443
[patent_doc_number] => 04554030
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-11-19
[patent_title] => 'Method of manufacturing a semiconductor device by means of a molecular beam technique'
[patent_app_type] => 1
[patent_app_number] => 6/585649
[patent_app_country] => US
[patent_app_date] => 1984-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 2615
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/554/04554030.pdf
[firstpage_image] =>[orig_patent_app_number] => 585649
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/585649 | Method of manufacturing a semiconductor device by means of a molecular beam technique | Mar 1, 1984 | Issued |
Array
(
[id] => 2181600
[patent_doc_number] => 04555273
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-11-26
[patent_title] => 'Furnace transient anneal process'
[patent_app_type] => 1
[patent_app_number] => 6/583560
[patent_app_country] => US
[patent_app_date] => 1984-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2766
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/555/04555273.pdf
[firstpage_image] =>[orig_patent_app_number] => 583560
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/583560 | Furnace transient anneal process | Feb 26, 1984 | Issued |
Array
(
[id] => 2163918
[patent_doc_number] => 04546537
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-10-15
[patent_title] => 'Method for producing a semiconductor device utilizing V-groove etching and thermal oxidation'
[patent_app_type] => 1
[patent_app_number] => 6/578592
[patent_app_country] => US
[patent_app_date] => 1984-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 3165
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 323
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/546/04546537.pdf
[firstpage_image] =>[orig_patent_app_number] => 578592
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/578592 | Method for producing a semiconductor device utilizing V-groove etching and thermal oxidation | Feb 9, 1984 | Issued |
Array
(
[id] => 2195000
[patent_doc_number] => 04502898
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-03-05
[patent_title] => 'Diffusion procedure for semiconductor compound'
[patent_app_type] => 1
[patent_app_number] => 6/563701
[patent_app_country] => US
[patent_app_date] => 1983-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 3240
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/502/04502898.pdf
[firstpage_image] =>[orig_patent_app_number] => 563701
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/563701 | Diffusion procedure for semiconductor compound | Dec 20, 1983 | Issued |
Array
(
[id] => 2227525
[patent_doc_number] => 04571275
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-02-18
[patent_title] => 'Method for minimizing autodoping during epitaxial deposition utilizing a graded pattern subcollector'
[patent_app_type] => 1
[patent_app_number] => 6/562927
[patent_app_country] => US
[patent_app_date] => 1983-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 18
[patent_no_of_words] => 3639
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 22
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/571/04571275.pdf
[firstpage_image] =>[orig_patent_app_number] => 562927
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/562927 | Method for minimizing autodoping during epitaxial deposition utilizing a graded pattern subcollector | Dec 18, 1983 | Issued |
Array
(
[id] => 2179743
[patent_doc_number] => 04504331
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-03-12
[patent_title] => 'Silicon dopant source in intermetallic semiconductor growth operations'
[patent_app_type] => 1
[patent_app_number] => 6/559583
[patent_app_country] => US
[patent_app_date] => 1983-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 1379
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/504/04504331.pdf
[firstpage_image] =>[orig_patent_app_number] => 559583
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/559583 | Silicon dopant source in intermetallic semiconductor growth operations | Dec 7, 1983 | Issued |
| 06/554793 | SINGLE CRYSTAL FILMS ON SEMICONDUCTOR COMPOUNDS | Nov 22, 1983 | Abandoned |
Array
(
[id] => 2218629
[patent_doc_number] => 04609413
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-09-02
[patent_title] => 'Method for manufacturing and epitaxially isolated semiconductor utilizing etch and refill technique'
[patent_app_type] => 1
[patent_app_number] => 6/553326
[patent_app_country] => US
[patent_app_date] => 1983-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 13
[patent_no_of_words] => 3505
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/609/04609413.pdf
[firstpage_image] =>[orig_patent_app_number] => 553326
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/553326 | Method for manufacturing and epitaxially isolated semiconductor utilizing etch and refill technique | Nov 17, 1983 | Issued |
Array
(
[id] => 2174405
[patent_doc_number] => 04529455
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-07-16
[patent_title] => 'Method for epitaxially growing Ge.sub.x Si.sub.1-x layers on Si utilizing molecular beam epitaxy'
[patent_app_type] => 1
[patent_app_number] => 6/546736
[patent_app_country] => US
[patent_app_date] => 1983-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 3731
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/529/04529455.pdf
[firstpage_image] =>[orig_patent_app_number] => 546736
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/546736 | Method for epitaxially growing Ge.sub.x Si.sub.1-x layers on Si utilizing molecular beam epitaxy | Oct 27, 1983 | Issued |
Array
(
[id] => 2179729
[patent_doc_number] => 04504330
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-03-12
[patent_title] => 'Optimum reduced pressure epitaxial growth process to prevent autodoping'
[patent_app_type] => 1
[patent_app_number] => 6/543555
[patent_app_country] => US
[patent_app_date] => 1983-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 1386
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/504/04504330.pdf
[firstpage_image] =>[orig_patent_app_number] => 543555
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/543555 | Optimum reduced pressure epitaxial growth process to prevent autodoping | Oct 18, 1983 | Issued |
Array
(
[id] => 2156260
[patent_doc_number] => 04509997
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-04-09
[patent_title] => 'Organometallic chemical vapor deposition of films utilizing organic heterocyclic compounds'
[patent_app_type] => 1
[patent_app_number] => 6/543003
[patent_app_country] => US
[patent_app_date] => 1983-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 2134
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/509/04509997.pdf
[firstpage_image] =>[orig_patent_app_number] => 543003
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/543003 | Organometallic chemical vapor deposition of films utilizing organic heterocyclic compounds | Oct 17, 1983 | Issued |
Array
(
[id] => 2197100
[patent_doc_number] => 04533410
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-08-06
[patent_title] => 'Process of vapor phase epitaxy of compound semiconductors'
[patent_app_type] => 1
[patent_app_number] => 6/542770
[patent_app_country] => US
[patent_app_date] => 1983-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 4436
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/533/04533410.pdf
[firstpage_image] =>[orig_patent_app_number] => 542770
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/542770 | Process of vapor phase epitaxy of compound semiconductors | Oct 16, 1983 | Issued |
Array
(
[id] => 2179717
[patent_doc_number] => 04504329
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-03-12
[patent_title] => 'Process for the epitaxial deposition of III-V compounds utilizing a binary alloy as the metallic source'
[patent_app_type] => 1
[patent_app_number] => 6/539603
[patent_app_country] => US
[patent_app_date] => 1983-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2938
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 323
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/504/04504329.pdf
[firstpage_image] =>[orig_patent_app_number] => 539603
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/539603 | Process for the epitaxial deposition of III-V compounds utilizing a binary alloy as the metallic source | Oct 5, 1983 | Issued |