Search

William Saba

Examiner (ID: 10944)

Most Active Art Unit
1104
Art Unit(s)
1104, 1101
Total Applications
280
Issued Applications
263
Pending Applications
0
Abandoned Applications
17

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2068176 [patent_doc_number] => 04443932 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-04-24 [patent_title] => 'Self-aligned oxide isolated process and device' [patent_app_type] => 1 [patent_app_number] => 6/339954 [patent_app_country] => US [patent_app_date] => 1982-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 21 [patent_no_of_words] => 5403 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/443/04443932.pdf [firstpage_image] =>[orig_patent_app_number] => 339954 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/339954
Self-aligned oxide isolated process and device Jan 17, 1982 Issued
Array ( [id] => 1999871 [patent_doc_number] => 04420874 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-12-20 [patent_title] => 'Method of producing an IIL semiconductor device utilizing self-aligned thickened oxide patterns' [patent_app_type] => 1 [patent_app_number] => 6/340286 [patent_app_country] => US [patent_app_date] => 1982-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 48 [patent_no_of_words] => 3654 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/420/04420874.pdf [firstpage_image] =>[orig_patent_app_number] => 340286 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/340286
Method of producing an IIL semiconductor device utilizing self-aligned thickened oxide patterns Jan 17, 1982 Issued
Array ( [id] => 2052580 [patent_doc_number] => 04426767 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-01-24 [patent_title] => 'Selective epitaxial etch planar processing for gallium arsenide semiconductors' [patent_app_type] => 1 [patent_app_number] => 6/338204 [patent_app_country] => US [patent_app_date] => 1982-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 20 [patent_no_of_words] => 2635 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/426/04426767.pdf [firstpage_image] =>[orig_patent_app_number] => 338204 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/338204
Selective epitaxial etch planar processing for gallium arsenide semiconductors Jan 10, 1982 Issued
06/336294 METHOD OF MAKING HIGH MOBILITY MULTILAYERED HETEROJUNCTION DEVICES EMPLOYING MODULATED DOPING Dec 30, 1981 Abandoned
Array ( [id] => 2065241 [patent_doc_number] => 04424621 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-01-10 [patent_title] => 'Method to fabricate stud structure for self-aligned metallization' [patent_app_type] => 1 [patent_app_number] => 6/335894 [patent_app_country] => US [patent_app_date] => 1981-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 5316 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/424/04424621.pdf [firstpage_image] =>[orig_patent_app_number] => 335894 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/335894
Method to fabricate stud structure for self-aligned metallization Dec 29, 1981 Issued
Array ( [id] => 2038759 [patent_doc_number] => 04412868 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-11-01 [patent_title] => 'Method of making integrated circuits utilizing ion implantation and selective epitaxial growth' [patent_app_type] => 1 [patent_app_number] => 6/333596 [patent_app_country] => US [patent_app_date] => 1981-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 3968 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/412/04412868.pdf [firstpage_image] =>[orig_patent_app_number] => 333596 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/333596
Method of making integrated circuits utilizing ion implantation and selective epitaxial growth Dec 22, 1981 Issued
Array ( [id] => 1999855 [patent_doc_number] => 04420872 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-12-20 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 6/333353 [patent_app_country] => US [patent_app_date] => 1981-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 17 [patent_no_of_words] => 4248 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/420/04420872.pdf [firstpage_image] =>[orig_patent_app_number] => 333353 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/333353
Method of manufacturing a semiconductor device Dec 21, 1981 Issued
Array ( [id] => 2091646 [patent_doc_number] => 04468851 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-09-04 [patent_title] => 'Process for making a heterojunction source-drain insulated gate field-effect transistors utilizing diffusion to form the lattice' [patent_app_type] => 1 [patent_app_number] => 6/330281 [patent_app_country] => US [patent_app_date] => 1981-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1803 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/468/04468851.pdf [firstpage_image] =>[orig_patent_app_number] => 330281 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/330281
Process for making a heterojunction source-drain insulated gate field-effect transistors utilizing diffusion to form the lattice Dec 13, 1981 Issued
06/328533 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE Dec 7, 1981 Abandoned
Array ( [id] => 2092182 [patent_doc_number] => 04428111 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-01-31 [patent_title] => 'Microwave transistor' [patent_app_type] => 1 [patent_app_number] => 6/327790 [patent_app_country] => US [patent_app_date] => 1981-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2519 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/428/04428111.pdf [firstpage_image] =>[orig_patent_app_number] => 327790 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/327790
Microwave transistor Dec 6, 1981 Issued
Array ( [id] => 2038219 [patent_doc_number] => 04404732 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-09-20 [patent_title] => 'Self-aligned extended epitaxy mesfet fabrication process' [patent_app_type] => 1 [patent_app_number] => 6/327832 [patent_app_country] => US [patent_app_date] => 1981-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2259 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/404/04404732.pdf [firstpage_image] =>[orig_patent_app_number] => 327832 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/327832
Self-aligned extended epitaxy mesfet fabrication process Dec 6, 1981 Issued
Array ( [id] => 2044686 [patent_doc_number] => 04416055 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-11-22 [patent_title] => 'Method of fabricating a monolithic integrated circuit structure' [patent_app_type] => 1 [patent_app_number] => 6/327383 [patent_app_country] => US [patent_app_date] => 1981-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3647 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 731 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/416/04416055.pdf [firstpage_image] =>[orig_patent_app_number] => 327383 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/327383
Method of fabricating a monolithic integrated circuit structure Dec 3, 1981 Issued
Array ( [id] => 2050523 [patent_doc_number] => 04408386 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-10-11 [patent_title] => 'Method of manufacturing semiconductor integrated circuit devices' [patent_app_type] => 1 [patent_app_number] => 6/326751 [patent_app_country] => US [patent_app_date] => 1981-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 35 [patent_no_of_words] => 4301 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/408/04408386.pdf [firstpage_image] =>[orig_patent_app_number] => 326751 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/326751
Method of manufacturing semiconductor integrated circuit devices Dec 1, 1981 Issued
Array ( [id] => 2100547 [patent_doc_number] => 04466173 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-08-21 [patent_title] => 'Methods for fabricating vertical channel buried grid field controlled devices including field effect transistors and field controlled thyristors utilizing etch and refill techniques' [patent_app_type] => 1 [patent_app_number] => 6/324328 [patent_app_country] => US [patent_app_date] => 1981-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 5189 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/466/04466173.pdf [firstpage_image] =>[orig_patent_app_number] => 324328 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/324328
Methods for fabricating vertical channel buried grid field controlled devices including field effect transistors and field controlled thyristors utilizing etch and refill techniques Nov 22, 1981 Issued
Array ( [id] => 1991609 [patent_doc_number] => 04380865 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-04-26 [patent_title] => 'Method of forming dielectrically isolated silicon semiconductor materials utilizing porous silicon formation' [patent_app_type] => 1 [patent_app_number] => 6/321263 [patent_app_country] => US [patent_app_date] => 1981-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 13 [patent_no_of_words] => 4740 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/380/04380865.pdf [firstpage_image] =>[orig_patent_app_number] => 321263 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/321263
Method of forming dielectrically isolated silicon semiconductor materials utilizing porous silicon formation Nov 12, 1981 Issued
Array ( [id] => 2125670 [patent_doc_number] => 04426237 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-01-17 [patent_title] => 'Volatile metal oxide suppression in molecular beam epitaxy systems' [patent_app_type] => 1 [patent_app_number] => 6/311091 [patent_app_country] => US [patent_app_date] => 1981-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2775 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/426/04426237.pdf [firstpage_image] =>[orig_patent_app_number] => 311091 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/311091
Volatile metal oxide suppression in molecular beam epitaxy systems Oct 12, 1981 Issued
Array ( [id] => 2043072 [patent_doc_number] => 04378630 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-04-05 [patent_title] => 'Process for fabricating a high performance PNP and NPN structure' [patent_app_type] => 1 [patent_app_number] => 6/309627 [patent_app_country] => US [patent_app_date] => 1981-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 24 [patent_no_of_words] => 5499 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 935 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/378/04378630.pdf [firstpage_image] =>[orig_patent_app_number] => 309627 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/309627
Process for fabricating a high performance PNP and NPN structure Oct 7, 1981 Issued
Array ( [id] => 2036767 [patent_doc_number] => 04403399 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-09-13 [patent_title] => 'Method of fabricating a vertical fuse utilizing epitaxial deposition and special masking' [patent_app_type] => 1 [patent_app_number] => 6/306226 [patent_app_country] => US [patent_app_date] => 1981-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 2306 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/403/04403399.pdf [firstpage_image] =>[orig_patent_app_number] => 306226 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/306226
Method of fabricating a vertical fuse utilizing epitaxial deposition and special masking Sep 27, 1981 Issued
Array ( [id] => 2038278 [patent_doc_number] => 04404738 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-09-20 [patent_title] => 'Method of fabricating an I.sup.2 L element and a linear transistor on one chip' [patent_app_type] => 1 [patent_app_number] => 6/305721 [patent_app_country] => US [patent_app_date] => 1981-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2533 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 364 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/404/04404738.pdf [firstpage_image] =>[orig_patent_app_number] => 305721 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/305721
Method of fabricating an I.sup.2 L element and a linear transistor on one chip Sep 24, 1981 Issued
Array ( [id] => 2006146 [patent_doc_number] => 04421576 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-12-20 [patent_title] => 'Method for forming an epitaxial compound semiconductor layer on a semi-insulating substrate' [patent_app_type] => 1 [patent_app_number] => 6/302196 [patent_app_country] => US [patent_app_date] => 1981-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1800 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/421/04421576.pdf [firstpage_image] =>[orig_patent_app_number] => 302196 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/302196
Method for forming an epitaxial compound semiconductor layer on a semi-insulating substrate Sep 13, 1981 Issued
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