William Shine

Array ( [id] => 20249671 [patent_doc_number] => 20250298540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => REDUNDANT COMPUTING ACROSS PLANES [patent_app_type] => utility [patent_app_number] => 19/170136 [patent_app_country] => US [patent_app_date] => 2025-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12676 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19170136 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20181250 [patent_doc_number] => 20250265208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => ELECTRONIC CONTROL UNIT AND CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 19/046249 [patent_app_country] => US [patent_app_date] => 2025-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4137 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19046249 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20043015 [patent_doc_number] => 20250181237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => Storage Optimization of CAT Table During Background Operations [patent_app_type] => utility [patent_app_number] => 19/044957 [patent_app_country] => US [patent_app_date] => 2025-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1179 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19044957 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20043306 [patent_doc_number] => 20250181528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => COMPUTING SYSTEM ARCHITECTURE HAVING EFFICIENT BUS CONNECTIONS [patent_app_type] => utility [patent_app_number] => 19/022389 [patent_app_country] => US [patent_app_date] => 2025-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 41827 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19022389 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20131064 [patent_doc_number] => 12373377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Protocol-aware provisioning of resource over CXL fabrics [patent_app_type] => utility [patent_app_number] => 19/017419 [patent_app_country] => US [patent_app_date] => 2025-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 79 [patent_figures_cnt] => 106 [patent_no_of_words] => 70932 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19017419 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20043305 [patent_doc_number] => 20250181527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => COMPUTING SYSTEM ARCHITECTURE HAVING EFFICIENT BUS CONNECTIONS [patent_app_type] => utility [patent_app_number] => 19/014838 [patent_app_country] => US [patent_app_date] => 2025-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 42944 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19014838 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20221723 [patent_doc_number] => 20250284654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => System for Multiple PCIe Hosts to Share SR-IOV Devices with Standard Host Drivers [patent_app_type] => utility [patent_app_number] => 19/011747 [patent_app_country] => US [patent_app_date] => 2025-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19011747 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20009662 [patent_doc_number] => 20250147884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => APPARATUS FOR MANAGING CACHE LOSS AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 19/003514 [patent_app_country] => US [patent_app_date] => 2024-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8151 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19003514 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19892030 [patent_doc_number] => 20250117342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => APPARATUS AND METHOD USING PLURALITY OF PHYSICAL ADDRESS SPACES [patent_app_type] => utility [patent_app_number] => 18/987328 [patent_app_country] => US [patent_app_date] => 2024-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24242 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18987328 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19891836 [patent_doc_number] => 20250117148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => THRESHOLD VOLTAGE BIN CALIBRATION AT MEMORY DEVICE POWER UP [patent_app_type] => utility [patent_app_number] => 18/982255 [patent_app_country] => US [patent_app_date] => 2024-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7041 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18982255 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20152155 [patent_doc_number] => 20250251993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => SHARED RESOURCE MANAGEMENT FOR MULTI-CORE SYSTEM [patent_app_type] => utility [patent_app_number] => 18/981503 [patent_app_country] => US [patent_app_date] => 2024-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5937 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18981503 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20052163 [patent_doc_number] => 20250190385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => ELECTRONIC SYSTEM HAVING AN INTEGRATED MASTER CIRCUIT AND AN INTEGRATED SLAVE CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/974946 [patent_app_country] => US [patent_app_date] => 2024-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1184 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18974946 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20043052 [patent_doc_number] => 20250181274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => DYNAMIC SELECTION OF CORES FOR PROCESSING RESPONSES [patent_app_type] => utility [patent_app_number] => 18/970574 [patent_app_country] => US [patent_app_date] => 2024-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2346 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18970574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20731994 [patent_doc_number] => 12639252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Control chip, operating circuit, and interface simulation method [patent_app_type] => utility [patent_app_number] => 18/963967 [patent_app_country] => US [patent_app_date] => 2024-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18963967 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20035071 [patent_doc_number] => 20250173293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => HUB DEVICE AND CONTROL SYSTEM [patent_app_type] => utility [patent_app_number] => 18/955302 [patent_app_country] => US [patent_app_date] => 2024-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1076 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18955302 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20043304 [patent_doc_number] => 20250181526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => COMPUTING SYSTEM ARCHITECTURE HAVING EFFICIENT BUS CONNECTIONS [patent_app_type] => utility [patent_app_number] => 18/955468 [patent_app_country] => US [patent_app_date] => 2024-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 41802 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -34 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18955468 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20037142 [patent_doc_number] => 20250175364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => SUBSCRIBER STATION AND METHOD FOR DETERMINISTIC COMMUNICATION IN A SERIAL BUS SYSTEM [patent_app_type] => utility [patent_app_number] => 18/947845 [patent_app_country] => US [patent_app_date] => 2024-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4318 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18947845 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19787197 [patent_doc_number] => 20250060876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => ADAPTIVE MEDIA MANAGEMENT FOR MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/933218 [patent_app_country] => US [patent_app_date] => 2024-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7899 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18933218 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19772208 [patent_doc_number] => 20250053634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => METHOD AND SYSTEM FOR IMPROVED DATA CONTROL AND ACCESS [patent_app_type] => utility [patent_app_number] => 18/931206 [patent_app_country] => US [patent_app_date] => 2024-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12559 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18931206 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19772209 [patent_doc_number] => 20250053635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => METHOD AND SYSTEM FOR IMPROVED DATA CONTROL AND ACCESS [patent_app_type] => utility [patent_app_number] => 18/931271 [patent_app_country] => US [patent_app_date] => 2024-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12559 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18931271 [rel_patent_id] =>[rel_patent_doc_number] =>)